Lines Matching +full:data +full:- +full:only

10     "BriefDescription": "Number of I-ERAT reloads"
25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued…
30 …"BriefDescription": "The processor's data cache was reloaded either shared or modified data from a…
35 …roup (Distant) due to a marked data side request. When using Radix Page Translation, this count ex…
40 …s L2 without conflict due to a data side request. When using Radix Page Translation, this count ex…
80 …data from another core's L2 on the same chip due to a marked data side request. When using Radix P…
85 …"BriefDescription": "Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst …
90 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
95 …(M) data from another core's L2 on the same chip due to a data side request. When using Radix Page…
110     "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K"
115 …on Mepf state. due to a marked data side request. When using Radix Page Translation, this count ex…
120 …"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radi…
160 …data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side r…
175 …ith dispatch conflict due to a data side request. When using Radix Page Translation, this count ex…
180 …thout conflict due to a marked data side request. When using Radix Page Translation, this count ex…
185 … Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache. This implies…
190 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
195 …and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch…
200     "BriefDescription": "Non-speculative icache miss, counted at completion"
205     "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 4K"
225 …thout conflict due to a marked data side request. When using Radix Page Translation, this count ex…
230     "BriefDescription": "Data PTEG reload"
235 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
240 …ded up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch…
245 …": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache"
250 …data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data s…
260 …data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data s…
265 …roup (Distant) due to a marked data side request. When using Radix Page Translation, this count ex…
270 …ts hit on Mepf state. due to a data side request. When using Radix Page Translation, this count ex…
280 … "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M (HPT mode) or 2M (Radix mode)"
285 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
305 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L2 on…
310 …data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked…
325 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
340 …: "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch…
365 …"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M (hpt mode) or 2M (radix…
380 …data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a ma…
390 …data from another core's L2/L3 on the same chip due to a marked data side request.. When using Rad…
395 …(S) data from another core's L2 on the same chip due to a data side request. When using Radix Page…
400 …data from another core's L3 on the same chip due to a marked data side request. When using Radix P…
425     "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K"
435 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
440 …"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction…
450 …ocal core's L2 due to a marked data side request. When using Radix Page Translation, this count ex…
475     "BriefDescription": "four flops operation (fdiv,fsqrt) Scalar Instructions only"
480 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without disp…
490 …ote or distant due to a marked data side request. When using Radix Page Translation, this count ex…
510 …mp prediction correct. Counts across all types of pumps for all data types excluding data prefetch…
515 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
530 …"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L2 on t…