Lines Matching +full:data +full:- +full:only
11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
23 …d Final Pump Scope was chip pump (prediction=correct) for all data types (demand load,data prefetc…
24 …and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all…
29 … "Initial and Final Pump Scope and data sourced across this scope was group pump for all data type…
30 …": "Initial and Final Pump Scope and data sourced across this scope was group pump for all data ty…
35 …d up either larger or smaller than Initial Pump Scope for all data types (demand load,data prefetc…
36 …"Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pum…
41 …Group) ended up larger than Initial Pump Scope (Chip) for all data types (demand load,data prefetc…
42 … data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initia…
47 … prediction correct. Counts across all types of pumps for all data types (demand load,data prefetc…
48 …ump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch…
53 …"Pump misprediction. Counts across all types of pumps for all data types (demand load,data prefetc…
54 …": "Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch…
59 …ption": "Initial and Final Pump Scope was system pump for all data types (demand load,data prefetc…
60 …: "Initial and Final Pump Scope and data sourced across this scope was system pump for all data ty…
65 …pe was System and it should have been smaller. Counts for all data types (demand load,data prefetc…
66 …ump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Fina…
71 … ended up larger than Initial Pump Scope (Chip/Group) for all data types (demand load,data prefetc…
72 …ump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for…
77 … conflict. The ifar logic will detect an interleave conflict and kill the data that was read that …
113 …ue to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that…
131 …cted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT …
161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
197 …ditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set …
203 …ditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set …
215 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
221 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
317 …all by stores this includes store agen finishes in pipe LS0/LS1 and store data finishes in LS2/LS3…
371 "BriefDescription": "IFU Finished a (non-branch) instruction",
377 … and Final Pump Scope was chip pump (prediction=correct) for either demand loads or data prefetch",
378 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
383 …data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or…
384 …'s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node…
389 …data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or G…
390 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
395 …The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Dista…
396 …tion": "The processor's data cache was reloaded from another chip's L4 on a different Node or Grou…
401 …The processor's data cache was reloaded from another chip's memory on the same Node or Group (Dist…
402 …tion": "The processor's data cache was reloaded from another chip's memory on the same Node or Gro…
407 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to either de…
408 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
413 …The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same …
414 …tion": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on t…
419 …"The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same c…
420 …ption": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on th…
425 …ion": "The processor's data cache was reloaded from a localtion other than the local core's L2 due…
426 …Description": "The processor's data cache was reloaded from a localtion other than the local core'…
431 …on": "The processor's data cache was reloaded from local core's L2 with load hit store conflict du…
432 …escription": "The processor's data cache was reloaded from local core's L2 with load hit store con…
437 …ption": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due t…
438 …icDescription": "The processor's data cache was reloaded from local core's L2 with dispatch confli…
443 …e processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf …
444 …on": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts …
449 …cription": "The processor's data cache was reloaded from local core's L2 without conflict due to e…
450 …ublicDescription": "The processor's data cache was reloaded from local core's L2 without conflict …
455 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to either de…
456 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either o…
461 …e processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the sam…
462 …on": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on…
467 …he processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same…
468 …ion": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on …
473 …The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same …
474 …tion": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on t…
479 …"The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same c…
480 …ption": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on th…
485 …ion": "The processor's data cache was reloaded from a localtion other than the local core's L3 due…
486 …Description": "The processor's data cache was reloaded from a localtion other than the local core'…
491 …ption": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due t…
492 …icDescription": "The processor's data cache was reloaded from local core's L3 with dispatch confli…
497 …e processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf …
498 …on": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit …
503 …cription": "The processor's data cache was reloaded from local core's L3 without conflict due to e…
504 …ublicDescription": "The processor's data cache was reloaded from local core's L3 without conflict …
509 …fDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to eith…
510 …"PublicDescription": "The processor's data cache was reloaded from the local chip's L4 cache due t…
515 …efDescription": "The processor's data cache was reloaded from the local chip's Memory due to eithe…
516 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to …
521 …he processor's data cache was reloaded from a memory location including L4 from local remote or di…
522 …ion": "The processor's data cache was reloaded from a memory location including L4 from local remo…
527 …data cache was reloaded either shared or modified data from another core's L2/L3 on a different ch…
528 …ssor's data cache was reloaded either shared or modified data from another core's L2/L3 on a diffe…
533 …ocessor's data cache was reloaded either shared or modified data from another core's L2/L3 on the …
534 … "The processor's data cache was reloaded either shared or modified data from another core's L2/L3…
539 …data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Gr…
540 …or's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node …
545 …data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Grou…
546 …sor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node o…
551 … "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remot…
552 …iption": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group…
557 …The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Rem…
558 …tion": "The processor's data cache was reloaded from another chip's memory on the same Node or Gro…
563 …and Final Pump Scope was group pump (prediction=correct) for either demand loads or data prefetch",
564 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pu…
569 …nded up either larger or smaller than Initial Pump Scope for either demand loads or data prefetch",
570 …"Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pum…
575 …e (Group) ended up larger than Initial Pump Scope (Chip) for either demand loads or data prefetch",
576 …"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pu…
581 …ump prediction correct. Counts across all types of pumps for either demand loads or data prefetch",
587 …": "Pump misprediction. Counts across all types of pumps for either demand loads or data prefetch",
593 …nd Final Pump Scope was system pump (prediction=correct) for either demand loads or data prefetch",
594 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system p…
599 …scope was System and it should have been smaller. Counts for either demand loads or data prefetch",
600 …ump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Fina…
605 …em) ended up larger than Initial Pump Scope (Chip/Group) for either demand loads or data prefetch",
606 …"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial P…
611 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
612 …tion": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on t…
617 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
618 …ption": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on th…
623 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
624 …on": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on…
629 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
630 …ion": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on …
635 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
636 …tion": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on t…
641 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
642 …ption": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on th…
647 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f…
648 "PublicDescription": "Data cache reload from memory (including L4)"
653 "BriefDescription": "DATA Cache collisions",
654 "PublicDescription": "DATA Cache collisions42"
695 "BriefDescription": "BCD->DPD opcode finish (denbcd, denbcdq)",
767 …ntry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to…
773 … Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to…
779 … loaded into the TLB from local core's L2 with load hit store conflict due to a data side request",
785 …ry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side request",
791 …ry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due …
797 …ntry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due …
803 …ntry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to…
809 … Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to…
815 …"BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing f…
1013 …"BriefDescription": "Group dispatched on a merged GCT empty. GCT entries can be merged only within…
1073 "BriefDescription": "GCT Utilization 11-14 entries",
1079 "BriefDescription": "GCT Utilization 15-17 entries",
1091 "BriefDescription": "GCT Utilization 1-2 entries",
1097 "BriefDescription": "GCT Utilization 3-6 entries",
1103 "BriefDescription": "GCT Utilization 7-10 entries",
1109 "BriefDescription": "Group experienced non-speculative branch redirect",
1110 "PublicDescription": "Group experienced Non-speculative br mispredicct"
1127 "BriefDescription": "Group experienced non-speculative I cache miss",
1128 "PublicDescription": "Group experi enced Non-specu lative I cache miss"
1248 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
1253 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1254 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1259 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1260 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1283 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1284 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1289 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1290 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1331 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1332 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1337 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1338 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1343 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1344 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1349 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1350 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1397 …"The processor's Instruction cache was reloaded either shared or modified data from another core's…
1398 …"The processor's Instruction cache was reloaded either shared or modified data from another core's…
1403 …"The processor's Instruction cache was reloaded either shared or modified data from another core's…
1404 …"The processor's Instruction cache was reloaded either shared or modified data from another core's…
1409 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1410 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1415 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1416 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1434 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pu…
1440 …"Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pum…
1446 …"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pu…
1464 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system p…
1470 …ump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Fina…
1476 …"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial P…
1487 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1488 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1493 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1494 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1499 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1500 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1505 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1506 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1511 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1512 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1517 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1518 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1535 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
1541 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
1559 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
1565 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
1571 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
1577 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
1583 "BriefDescription": "All i-side dispatch attempts",
1589 …"BriefDescription": "All i-side dispatch attempts that failed due to a addr collision with another…
1595 …"BriefDescription": "All i-side dispatch attempts that failed due to a reason other than addrs col…
1601 …"BriefDescription": "valid when first beat of data comes in for an i-side fetch where data came fr…
1727 …"BriefDescription": "valid when first beat of data comes in for an L1pref where data came from mem…
1739 "BriefDescription": "L2 Castouts - Modified (M, Mu, Me)",
1745 "BriefDescription": "L2 Castouts - Shared (T, Te, Si, S)",
1775 "BriefDescription": "L2 guess grp and guess was correct (data intra-6chip AND ^on-chip)",
1781 "BriefDescription": "L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)",
1793 …"BriefDescription": "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)",
1799 …"BriefDescription": "All successful i-side dispatches that were an L2miss for this thread (exclude…
1805 "BriefDescription": "All successful D-side Load dispatches for this thread",
1823 "BriefDescription": "All successful D-Side Load dispatches that were an L2miss for this thread",
1829 "BriefDescription": "L2 guess loc and guess was correct (ie data local)",
1835 "BriefDescription": "L2 guess loc and guess was not correct (ie data not on chip)",
1913 "BriefDescription": "All successful D-side store dispatches for this thread",
1931 "BriefDescription": "All successful D-side store dispatches for this thread that were L2 Miss",
1937 "BriefDescription": "L2 guess sys and guess was correct (ie data beyond-6chip)",
1943 "BriefDescription": "L2 guess sys and guess was not correct (ie data ^beyond-6chip)",
2027 "BriefDescription": "Initial scope=group and data from same group (near) (pred successful)",
2033 "BriefDescription": "Initial scope=group but data from local node. Predition too high",
2039 …"BriefDescription": "Initial scope=group but data from outside group (far or rem). Prediction too …
2093 … "BriefDescription": "initial scope=node/chip and data from local node (local) (pred successful)",
2099 …"BriefDescription": "Initial scope=node but data from out side local node (near or far or rem). Pr…
2135 "BriefDescription": "lco sent with data port 0",
2213 "BriefDescription": "lco sent with data port 1",
2369 "BriefDescription": "Data stream touchto L3",
2375 …"BriefDescription": "Initial scope=system and data from outside group (far or rem)(pred successful…
2381 "BriefDescription": "Initial scope=system but data from local or near. Predction too high",
2453 "BriefDescription": "LS0 L1 cache data prefetches",
2454 "PublicDescription": "LS0 L1 cache data prefetches42"
2471 "BriefDescription": "LS1 L1 cache data prefetches",
2472 "PublicDescription": "LS1 L1 cache data prefetches42"
2525 "BriefDescription": "LS0 Non-cachable Loads counted at finish",
2526 "PublicDescription": "LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads"
2543 "BriefDescription": "LS0 SRQ forwarded data to a load",
2544 "PublicDescription": "LS0 SRQ forwarded data to a loadLSU0 SRQ store forwarded"
2555 …"BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is …
2556 …"PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is…
2615 "BriefDescription": "LS1 Non-cachable Loads counted at finish",
2616 "PublicDescription": "LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads"
2633 "BriefDescription": "LS1 SRQ forwarded data to a load",
2634 "PublicDescription": "LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded"
2645 …"BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is …
2646 …"PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is…
2723 "BriefDescription": "LS2 SRQ forwarded data to a load",
2724 "PublicDescription": "LS2 SRQ forwarded data to a load42"
2729 …"BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is …
2730 …"PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is…
2807 "BriefDescription": "LS3 SRQ forwarded data to a load",
2808 "PublicDescription": "LS3 SRQ forwarded data to a load42"
2813 …"BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is …
2814 …"PublicDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is…
2867 "BriefDescription": "FPU loads only on LS2/LS3 ie LU0/LU1",
2873 "BriefDescription": "Vector loads can issue only on LS2/LS3",
2885 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
2903 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
2933 "BriefDescription": "count at finish so can return only on ls0 or ls1",
2939 "BriefDescription": "Non-cachable Stores sent to nest",
2940 "PublicDescription": "Non-cachable Stores sent to nest42"
2963 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
3023 "BriefDescription": "IFU non-branch finished",
3024 "PublicDescription": "IFU non-branch marked instruction finished"
3029 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
3035 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L2 on…
3041 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
3047 …"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L2 on t…
3053 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
3059 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's ECO L…
3065 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
3071 …"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 …
3077 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
3083 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L3 on…
3089 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
3095 …"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L3 on t…
3101 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f…
3107 …y was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a …
3113 …try was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a …
3119 … into the TLB from local core's L2 with load hit store conflict due to a marked data side request",
3125 …loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side request",
3131 …was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to …
3137 …y was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to …
3143 …y was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a …
3149 …try was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a …
3450 "PublicDescription": "Cycles run latch is set and core is in SMT2-shared mode"
3455 "BriefDescription": "Cycles run latch is set and core is in SMT2-split mode",
3473 "BriefDescription": "Store-Hit-Load Table Entry Created",
3479 "BriefDescription": "Store-Hit-Load Table Read Hit with entry Enabled",
3485 …"BriefDescription": "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to …
3707 "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)",
3725 "BriefDescription": "TM Store (fav or non-fav) caused another thread to fail",
3731 "BriefDescription": "TM Store (fav or non-fav) ran into conflict (failed)",
3774 …tr IOP, multiplied by #vector elements according to route( eg x1, x2, x4) Only if instr sends fini…
3851 …"BriefDescription": "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!",
3863 "BriefDescription": "four flops operation (fdiv,fsqrt) Scalar Instructions only!",
4001 …"BriefDescription": "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!",
4013 "BriefDescription": "four flops operation (fdiv,fsqrt) Scalar Instructions only!",