Lines Matching +full:co +full:- +full:processor

11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re…
161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
197 …ional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set thi…
203 …ional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set thi…
215 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
221 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
257     "BriefDescription": "Completion stall due to CO q full",
341 …"BriefDescription": "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample po…
347 …"BriefDescription": "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample po…
353     "BriefDescription": "CO dispatch failed due to all CO machines being busy",
359     "BriefDescription": "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3)",
365 …ous 16 cycle(2to1) window where this signals rotates thru sampling each L2 CO machine busy. PMU us…
371     "BriefDescription": "IFU Finished a (non-branch) instruction",
383 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
384 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
389 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
390 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
395 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
396 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
401 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
402 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…
407 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to either de…
408 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
413 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
414 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
419 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
420 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another co…
425 …"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local…
426 …"PublicDescription": "The processor's data cache was reloaded from a localtion other than the loca…
431 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
432 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 with load hit s…
437 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch co…
438 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 with dispatch c…
443 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without disp…
444 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 hit without dis…
449 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict…
450 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 without conflic…
455 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to either de…
456 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either o…
461 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
462 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
467 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
468 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another co…
473 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
474 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
479 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
480 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another co…
485 …"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local…
486 …"PublicDescription": "The processor's data cache was reloaded from a localtion other than the loca…
491 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co…
492 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 with dispatch c…
497 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch…
498 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 without dispatc…
503 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict…
504 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 without conflic…
509 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to…
510 …"PublicDescription": "The processor's data cache was reloaded from the local chip's L4 cache due t…
515 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to e…
516 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to …
521 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f…
522 …"PublicDescription": "The processor's data cache was reloaded from a memory location including L4 …
527 …"BriefDescription": "The processor's data cache was reloaded either shared or modified data from a…
528 …"PublicDescription": "The processor's data cache was reloaded either shared or modified data from …
533 …"BriefDescription": "The processor's data cache was reloaded either shared or modified data from a…
534 …"PublicDescription": "The processor's data cache was reloaded either shared or modified data from …
539 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
540 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
545 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
546 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
551 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…
552 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on the same N…
557 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
558 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…
611 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
612 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
617 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
618 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another co…
623 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
624 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
629 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
630 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another co…
635 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
636 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
641 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
642 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another co…
647 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f…
695     "BriefDescription": "BCD->DPD opcode finish (denbcd, denbcdq)",
815 …"BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing f…
1073     "BriefDescription": "GCT Utilization 11-14 entries",
1079     "BriefDescription": "GCT Utilization 15-17 entries",
1091     "BriefDescription": "GCT Utilization 1-2 entries",
1097     "BriefDescription": "GCT Utilization 3-6 entries",
1103     "BriefDescription": "GCT Utilization 7-10 entries",
1109     "BriefDescription": "Group experienced non-speculative branch redirect",
1110     "PublicDescription": "Group experienced Non-speculative br mispredicct"
1127     "BriefDescription": "Group experienced non-speculative I cache miss",
1128     "PublicDescription": "Group experi enced Non-specu lative I cache miss"
1253 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1254 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1259 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1260 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1265 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
1266 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
1271 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
1272 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…
1277 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to in…
1278 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to e…
1283 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1284 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1289 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1290 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1295 …"BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than th…
1296 …"PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than t…
1301 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with load…
1302 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 with loa…
1307 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp…
1308 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 with dis…
1313 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 hit witho…
1314 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 hit with…
1319 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without c…
1320 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 without …
1325 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to in…
1326 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to e…
1331 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1332 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1337 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1338 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1343 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1344 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1349 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1350 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1355 …"BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than th…
1356 …"PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than t…
1361 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with disp…
1362 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 with dis…
1367 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without d…
1368 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 without …
1373 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without c…
1374 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 without …
1379 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache…
1380 …"PublicDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cach…
1385 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d…
1386 …"PublicDescription": "The processor's Instruction cache was reloaded from the local chip's Memory …
1391 …"BriefDescription": "The processor's Instruction cache was reloaded from a memory location includi…
1392 …"PublicDescription": "The processor's Instruction cache was reloaded from a memory location includ…
1397 …"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data…
1398 …"PublicDescription": "The processor's Instruction cache was reloaded either shared or modified dat…
1403 …"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data…
1404 …"PublicDescription": "The processor's Instruction cache was reloaded either shared or modified dat…
1409 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1410 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1415 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1416 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1421 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the …
1422 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the…
1427 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
1428 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…
1487 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1488 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1493 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1494 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1499 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1500 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1505 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1506 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1511 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
1512 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
1517 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
1518 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
1583     "BriefDescription": "All i-side dispatch attempts",
1589 …"BriefDescription": "All i-side dispatch attempts that failed due to a addr collision with another…
1595 …"BriefDescription": "All i-side dispatch attempts that failed due to a reason other than addrs col…
1601 …"BriefDescription": "valid when first beat of data comes in for an i-side fetch where data came fr…
1739     "BriefDescription": "L2 Castouts - Modified (M, Mu, Me)",
1745     "BriefDescription": "L2 Castouts - Shared (T, Te, Si, S)",
1775     "BriefDescription": "L2 guess grp and guess was correct (data intra-6chip AND ^on-chip)",
1781     "BriefDescription": "L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)",
1793 …"BriefDescription": "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)",
1799 …"BriefDescription": "All successful i-side dispatches that were an L2miss for this thread (exclude…
1805     "BriefDescription": "All successful D-side Load dispatches for this thread",
1823     "BriefDescription": "All successful D-Side Load dispatches that were an L2miss for this thread",
1847 …"BriefDescription": "L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
1865 …"BriefDescription": "L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ…
1913     "BriefDescription": "All successful D-side store dispatches for this thread",
1931     "BriefDescription": "All successful D-side store dispatches for this thread that were L2 Miss",
1937     "BriefDescription": "L2 guess sys and guess was correct (ie data beyond-6chip)",
1943     "BriefDescription": "L2 guess sys and guess was not correct (ie data ^beyond-6chip)",
1985     "BriefDescription": "rotating sample of 16 CI or CO actives",
1997     "BriefDescription": "lifetime, sample of CO machine 0 valid",
2003     "BriefDescription": "lifetime, sample of CO machine 0 valid",
2009     "BriefDescription": "L3 CO to L3.1 OR of port 0 and 1 ( lossy)",
2021     "BriefDescription": "L3 CO to memory OR of port 0 and 1 ( lossy)",
2111     "BriefDescription": "l3 CO to L3.1 (lco) port 0",
2117     "BriefDescription": "l3 CO to memory port 0",
2123     "BriefDescription": "L3 CO received retry port 0",
2189     "BriefDescription": "l3 CO to L3.1 (lco) port 1",
2195     "BriefDescription": "l3 CO to memory port 1",
2201     "BriefDescription": "L3 CO received retry port 1",
2525     "BriefDescription": "LS0 Non-cachable Loads counted at finish",
2526     "PublicDescription": "LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads"
2615     "BriefDescription": "LS1 Non-cachable Loads counted at finish",
2616     "PublicDescription": "LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads"
2885 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
2903 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
2939     "BriefDescription": "Non-cachable Stores sent to nest",
2940     "PublicDescription": "Non-cachable Stores sent to nest42"
2963 …"BriefDescription": "Per thread - use edge detect to count allocates On a per thread basis, level …
3023     "BriefDescription": "IFU non-branch finished",
3024     "PublicDescription": "IFU non-branch marked instruction finished"
3029 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
3041 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
3053 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
3065 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
3077 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
3089 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
3101 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f…
3450     "PublicDescription": "Cycles run latch is set and core is in SMT2-shared mode"
3455     "BriefDescription": "Cycles run latch is set and core is in SMT2-split mode",
3473     "BriefDescription": "Store-Hit-Load Table Entry Created",
3479     "BriefDescription": "Store-Hit-Load Table Read Hit with entry Enabled",
3485 …"BriefDescription": "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to …
3629     "BriefDescription": "l3 tm cam overflow during L2 co of SC",
3707     "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)",
3725     "BriefDescription": "TM Store (fav or non-fav) caused another thread to fail",
3731     "BriefDescription": "TM Store (fav or non-fav) ran into conflict (failed)",