Lines Matching +full:system +full:- +full:cache +full:- +full:controller

44 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
59 .%T "Volume 3B: System Programming Guide, Part 2"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
93 Configure the PMC to count the number of de-asserted to asserted
108 .Bl -tag -width indent
142 Counts the number GQ read tracker entries for which a full cache line read
145 to obtain the average cache line read L3 miss latency.
147 cache line has missed.
149 the cache line has missed is the average L3 hit latency.
150 The total L3 cache line read miss latency is the hit latency + L3 miss
195 Cycles GQ L3 input data port is busy importing data from the Last Level Cache.
214 Cycles GQ L3 output data port is busy sending data to the Last Level Cache.
223 referenced cache line.
231 L3 has the referenced cache line in the E state.
232 The L3 cache line state is changed to the S state and the line is forwarded
237 has the referenced cache line in the M state.
238 The L3 cache line state is invalidated and the line is forwarded to the
250 referenced cache line.
258 has the referenced cache line in the E state.
259 The L3 cache line state is changed to the S state and the line is forwarded
264 has the referenced cache line in the M state.
265 The L3 cache line state is invalidated and the line is forwarded to the
308 The only time a cache line is allocated in the M state is when the
325 When the victim cache line is in M state, the line is written to its home cache agent
344 Counts the number of remote snoops that have requested a cache line be set
348 Counts the number of remote snoops that have requested a cache line be set
352 Counts the number of remote snoops that have requested a cache line be set
357 Counts the number of remote snoops that have requested a cache line be set
362 Counts the number of remote snoops that have requested a cache line be set
367 Counts the number of remote snoops that have requested a cache line be set
372 Counts the number of remote snoops that have requested a cache line be set
377 Counts the number of remote snoops that have requested a cache line be set
382 Counts the number of remote snoops that have requested a cache line be set
387 Counts the number of remote snoops that have requested a cache line be set
468 Counts number or requests to the Quickpath Memory Controller that bypass the
498 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
502 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
506 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
510 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
514 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
518 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
546 Counts the number of Quickpath Memory Controller channel 0 medium and low
552 Counts the number of Quickpath Memory Controller channel 1 medium and low
558 Counts the number of Quickpath Memory Controller channel 2 medium and low
564 Counts the number of Quickpath Memory Controller medium and low priority read requests.
569 Counts the number of Quickpath Memory Controller channel 0 high priority
573 Counts the number of Quickpath Memory Controller channel 1 high priority
577 Counts the number of Quickpath Memory Controller channel 2 high priority
581 Counts the number of Quickpath Memory Controller high priority isochronous
585 Counts the number of Quickpath Memory Controller channel 0 critical priority
589 Counts the number of Quickpath Memory Controller channel 1 critical priority
593 Counts the number of Quickpath Memory Controller channel 2 critical priority
597 Counts the number of Quickpath Memory Controller critical priority
601 Counts number of full cache line writes to DRAM channel 0.
604 Counts number of full cache line writes to DRAM channel 1.
607 Counts number of full cache line writes to DRAM channel 2.
610 Counts number of full cache line writes to DRAM.
613 Counts number of partial cache line writes to DRAM channel 0.
616 Counts number of partial cache line writes to DRAM channel 1.
619 Counts number of partial cache line writes to DRAM channel 2.
622 Counts number of partial cache line writes to DRAM.
762 Counts cycles the Quickpath outbound link 0 non-data response virtual
780 Counts cycles the Quickpath outbound link 1 non-data response virtual
804 Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual
810 Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual
822 Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual
828 Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual
924 where the command issued used the auto-precharge (auto page close) mode.
931 where the command issued used the auto-precharge (auto page close) mode.
938 where the command issued used the auto-precharge (auto page close) mode.
945 where the command issued used the auto-precharge (auto page close) mode.
952 where the command issued used the auto-precharge (auto page close) mode.
959 where the command issued used the auto-precharge (auto page close) mode.
978 Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close
983 Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close
988 Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close
1029 Number of system assertions of PROCHOT indicating the entire processor has
1034 system asserting PROCHOT the entire processor has exceeded the thermal
1039 system asserting PROCHOT the entire processor has exceeded the thermal
1044 system asserting PROCHOT the entire processor has exceeded the thermal
1049 system asserting PROCHOT the entire processor has exceeded the thermal