Lines Matching +full:read +full:- +full:1

6 .\" 1. Redistributions of source code must retain the above copyright
44 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
93 Configure the PMC to count the number of de-asserted to asserted
108 .Bl -tag -width indent
111 Uncore cycles Global Queue read tracker is full.
121 Uncore cycles were Global Queue read tracker has at least one valid entry.
131 Increments the number of queue entries (code read, data read, and RFOs) in
133 The GQ read tracker allocate to deallocate occupancy count is divided by the
134 count to obtain the average read tracker latency.
138 The GQ read tracker allocate to deallocate occupancy count is divided by
139 the count to obtain the average read tracker latency.
142 Counts the number GQ read tracker entries for which a full cache line read
144 The GQ read tracker L3 miss to fill occupancy count is divided by this count
145 to obtain the average cache line read L3 miss latency.
148 The time between a GQ read tracker allocation and the L3 determining that
150 The total L3 cache line read miss latency is the hit latency + L3 miss
154 Counts the number of GQ read tracker entries that are allocated in the read
156 The GQ read tracker L3 hit occupancy count is divided by this count to obtain the average L3 hit la…
159 Counts the number of GQ read tracker entries that are allocated in the read
161 The GQ read tracker L3 miss to RTID acquired occupancy count is
162 divided by this count to obtain the average latency for a read L3 miss to
204 Cycles GQ Core 1 and 3 input data port is busy importing data from processor
205 cores 1 and 3.
230 Number of responses to code or data read snoops to the local home that the
236 Number of responses to read invalidate snoops to the local home that the L3
245 Number of responses to code or data read snoops to the local home that the
257 Number of responses to code or data read snoops to a remote home that the L3
263 Number of responses to read invalidate snoops to a remote home that the L3
272 Number of responses to code or data read snoops to a remote home that the L3
277 .It Li L3_HITS.READ
279 Number of code read, data read and RFO requests that hit in the L3.
291 .It Li L3_MISS.READ
293 Number of code read, data read and RFO requests that miss the L3.
309 line was forwarded in M state is forwarded due to a Snoop Read Invalidate Own request.
340 .Pq Event 0BH , Umask 1FH
364 Requires writing MSR 301H with mask = 1H
384 Requires writing MSR 301H with mask = 1H
392 Counts number of Quickpath Home Logic read requests from the IOH.
398 Counts number of Quickpath Home Logic read requests from a remote socket.
404 Counts number of Quickpath Home Logic read requests from the local socket.
432 QHL IOH tracker allocate to deallocate read occupancy.
435 QHL remote tracker allocate to deallocate read occupancy.
438 QHL local tracker allocate to deallocate read occupancy.
471 For remote requests, only read requests can be bypassed.
472 .It Li QMC_ISOC_FULL.READ.CH0
475 occupied with isochronous read requests.
476 .It Li QMC_ISOC_FULL.READ.CH1
478 Counts cycles all the entries in the DRAM channel 1 high priority queue are
479 occupied with isochronous read requests.
480 .It Li QMC_ISOC_FULL.READ.CH2
483 occupied with isochronous read requests.
490 Counts cycles all the entries in the DRAM channel 1 high priority queue are
496 .It Li QMC_BUSY.READ.CH0
498 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
499 read request to DRAM channel 0.
500 .It Li QMC_BUSY.READ.CH1
502 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
503 read request to DRAM channel 1.
504 .It Li QMC_BUSY.READ.CH2
506 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
507 read request to DRAM channel 2.
510 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
514 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
515 write request to DRAM channel 1.
518 Counts cycles where Quickpath Memory Controller has at least 1 outstanding
522 IMC channel 0 normal read request occupancy.
525 IMC channel 1 normal read request occupancy.
528 IMC channel 2 normal read request occupancy.
531 Normal read request occupancy for any channel.
534 IMC channel 0 issoc read request occupancy.
537 IMC channel 1 issoc read request occupancy.
540 IMC channel 2 issoc read request occupancy.
543 IMC issoc read request occupancy.
547 priority read requests.
548 The QMC channel 0 normal read occupancy divided by this count provides the
549 average QMC channel 0 read latency.
552 Counts the number of Quickpath Memory Controller channel 1 medium and low
553 priority read requests.
554 The QMC channel 1 normal read occupancy divided by this count provides the
555 average QMC channel 1 read latency.
559 priority read requests.
560 The QMC channel 2 normal read occupancy divided by this count provides the
561 average QMC channel 2 read latency.
564 Counts the number of Quickpath Memory Controller medium and low priority read requests.
565 The QMC normal read occupancy divided by this count provides the average
566 QMC read latency.
570 isochronous read requests.
573 Counts the number of Quickpath Memory Controller channel 1 high priority
574 isochronous read requests.
578 isochronous read requests.
582 read requests.
586 isochronous read requests.
589 Counts the number of Quickpath Memory Controller channel 1 critical priority
590 isochronous read requests.
594 isochronous read requests.
598 isochronous read requests.
604 Counts number of full cache line writes to DRAM channel 1.
616 Counts number of partial cache line writes to DRAM channel 1.
628 Counts number of DRAM channel 1 cancel requests.
645 Counts number of DRAM channel 1 priority updates.
670 Counts number of IMC DRAM channel 1 retries.
699 (write after read) conflicts.
704 ordering (write after read) conflicts.
709 ordering (write after read) conflicts.
762 Counts cycles the Quickpath outbound link 0 non-data response virtual
768 Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled
774 Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled
780 Counts cycles the Quickpath outbound link 1 non-data response virtual
792 Counts cycles the Quickpath outbound link 1 virtual channels are stalled due
804 Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual
810 Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual
816 Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is
822 Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual
828 Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual
840 Counts cycles the Quickpath outbound link 1 virtual channels are stalled due
855 link 1 is full.
859 link 1 is busy.
868 1 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT)
872 Counts number of DRAM Channel 0 open commands issued either for read or write.
873 To read or write data, the referenced DRAM page must first be opened.
876 Counts number of DRAM Channel 1 open commands issued either for read or write.
877 To read or write data, the referenced DRAM page must first be opened.
880 Counts number of DRAM Channel 2 open commands issued either for read or write.
881 To read or write data, the referenced DRAM page must first be opened.
888 DRAM channel 1 command issued to CLOSE a page due to page idle timer expiration.
904 Counts the number of precharges (PRE) that were issued to DRAM channel 1
920 Counts the number of times a read CAS command was issued on DRAM channel 0.
923 Counts the number of times a read CAS command was issued on DRAM channel 0
924 where the command issued used the auto-precharge (auto page close) mode.
927 Counts the number of times a read CAS command was issued on DRAM channel 1.
930 Counts the number of times a read CAS command was issued on DRAM channel 1
931 where the command issued used the auto-precharge (auto page close) mode.
934 Counts the number of times a read CAS command was issued on DRAM channel 2.
937 Counts the number of times a read CAS command was issued on DRAM channel 2
938 where the command issued used the auto-precharge (auto page close) mode.
945 where the command issued used the auto-precharge (auto page close) mode.
948 Counts the number of times a write CAS command was issued on DRAM channel 1.
951 Counts the number of times a write CAS command was issued on DRAM channel 1
952 where the command issued used the auto-precharge (auto page close) mode.
959 where the command issued used the auto-precharge (auto page close) mode.
968 Counts number of DRAM channel 1 refresh commands.
978 Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close
983 Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close
988 Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close
1001 Cycles that the PCU records that core 1 is above the thermal throttling
1017 Cycles that the PCU records that core 1 is in the power throttled state due
1038 Cycles that the PCU records that core 1 is a low power state due to the
1056 Uncore cycles that core 1 is operating in turbo mode.