Lines Matching +full:channel +full:- +full:3

44 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
54 .Xr pmc_cpuinfo 3 .
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
59 .%T "Volume 3B: System Programming Guide, Part 2"
60 .%N "Order Number: 253669-033US"
66 .Xr pmc.ucf 3 .
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
93 Configure the PMC to count the number of de-asserted to asserted
108 .Bl -tag -width indent
204 Cycles GQ Core 1 and 3 input data port is busy importing data from processor
205 cores 1 and 3.
445 .It Li QHL_ADDRESS_CONFLICTS.3WAY
447 Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 conflicts.
455 A max of 3 requests can be in conflict.
460 A max of 3 requests can be in conflict.
465 A max of 3 requests can be in conflict.
474 Counts cycles all the entries in the DRAM channel 0 high priority queue are
478 Counts cycles all the entries in the DRAM channel 1 high priority queue are
482 Counts cycles all the entries in the DRAM channel 2 high priority queue are
486 Counts cycles all the entries in the DRAM channel 0 high priority queue are
490 Counts cycles all the entries in the DRAM channel 1 high priority queue are
494 Counts cycles all the entries in the DRAM channel 2 high priority queue are
499 read request to DRAM channel 0.
503 read request to DRAM channel 1.
507 read request to DRAM channel 2.
511 write request to DRAM channel 0.
515 write request to DRAM channel 1.
519 write request to DRAM channel 2.
522 IMC channel 0 normal read request occupancy.
525 IMC channel 1 normal read request occupancy.
528 IMC channel 2 normal read request occupancy.
531 Normal read request occupancy for any channel.
534 IMC channel 0 issoc read request occupancy.
537 IMC channel 1 issoc read request occupancy.
540 IMC channel 2 issoc read request occupancy.
546 Counts the number of Quickpath Memory Controller channel 0 medium and low
548 The QMC channel 0 normal read occupancy divided by this count provides the
549 average QMC channel 0 read latency.
552 Counts the number of Quickpath Memory Controller channel 1 medium and low
554 The QMC channel 1 normal read occupancy divided by this count provides the
555 average QMC channel 1 read latency.
558 Counts the number of Quickpath Memory Controller channel 2 medium and low
560 The QMC channel 2 normal read occupancy divided by this count provides the
561 average QMC channel 2 read latency.
569 Counts the number of Quickpath Memory Controller channel 0 high priority
573 Counts the number of Quickpath Memory Controller channel 1 high priority
577 Counts the number of Quickpath Memory Controller channel 2 high priority
585 Counts the number of Quickpath Memory Controller channel 0 critical priority
589 Counts the number of Quickpath Memory Controller channel 1 critical priority
593 Counts the number of Quickpath Memory Controller channel 2 critical priority
601 Counts number of full cache line writes to DRAM channel 0.
604 Counts number of full cache line writes to DRAM channel 1.
607 Counts number of full cache line writes to DRAM channel 2.
613 Counts number of partial cache line writes to DRAM channel 0.
616 Counts number of partial cache line writes to DRAM channel 1.
619 Counts number of partial cache line writes to DRAM channel 2.
625 Counts number of DRAM channel 0 cancel requests.
628 Counts number of DRAM channel 1 cancel requests.
631 Counts number of DRAM channel 2 cancel requests.
637 Counts number of DRAM channel 0 priority updates.
645 Counts number of DRAM channel 1 priority updates.
652 Counts number of DRAM channel 2 priority updates.
666 Counts number of IMC DRAM channel 0 retries.
670 Counts number of IMC DRAM channel 1 retries.
674 Counts number of IMC DRAM channel 2 retries.
678 Counts number of IMC DRAM retries from any channel.
750 Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled
753 for arbitration because another virtual channel is getting arbitrated.
756 Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled
759 for arbitration because another virtual channel is getting arbitrated.
762 Counts cycles the Quickpath outbound link 0 non-data response virtual
763 channel is stalled due to lack of a VNA and VN0 credit.
765 for arbitration because another virtual channel is getting arbitrated.
768 Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled
771 for arbitration because another virtual channel is getting arbitrated.
774 Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled
777 for arbitration because another virtual channel is getting arbitrated.
780 Counts cycles the Quickpath outbound link 1 non-data response virtual
781 channel is stalled due to lack of a VNA and VN0 credit.
783 for arbitration because another virtual channel is getting arbitrated.
789 for arbitration because another virtual channel is getting arbitrated.
795 for arbitration because another virtual channel is getting arbitrated.
798 Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is
801 for arbitration because another virtual channel is getting arbitrated.
804 Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual
805 channel is stalled due to lack of VNA and VN0 credits.
807 for arbitration because another virtual channel is getting arbitrated.
810 Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual
811 channel is stalled due to lack of VNA and VN0 credits.
813 for arbitration because another virtual channel is getting arbitrated.
816 Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is
819 for arbitration because another virtual channel is getting arbitrated.
822 Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual
823 channel is stalled due to lack of VNA and VN0 credits.
825 for arbitration because another virtual channel is getting arbitrated.
828 Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual
829 channel is stalled due to lack of VNA and VN0 credits.
831 for arbitration because another virtual channel is getting arbitrated.
837 for arbitration because another virtual channel is getting arbitrated.
843 for arbitration because another virtual channel is getting arbitrated.
872 Counts number of DRAM Channel 0 open commands issued either for read or write.
876 Counts number of DRAM Channel 1 open commands issued either for read or write.
880 Counts number of DRAM Channel 2 open commands issued either for read or write.
884 DRAM channel 0 command issued to CLOSE a page due to page idle timer expiration.
888 DRAM channel 1 command issued to CLOSE a page due to page idle timer expiration.
892 DRAM channel 2 command issued to CLOSE a page due to page idle timer expiration.
896 Counts the number of precharges (PRE) that were issued to DRAM channel 0
904 Counts the number of precharges (PRE) that were issued to DRAM channel 1
912 Counts the number of precharges (PRE) that were issued to DRAM channel 2
920 Counts the number of times a read CAS command was issued on DRAM channel 0.
923 Counts the number of times a read CAS command was issued on DRAM channel 0
924 where the command issued used the auto-precharge (auto page close) mode.
927 Counts the number of times a read CAS command was issued on DRAM channel 1.
930 Counts the number of times a read CAS command was issued on DRAM channel 1
931 where the command issued used the auto-precharge (auto page close) mode.
934 Counts the number of times a read CAS command was issued on DRAM channel 2.
937 Counts the number of times a read CAS command was issued on DRAM channel 2
938 where the command issued used the auto-precharge (auto page close) mode.
941 Counts the number of times a write CAS command was issued on DRAM channel 0.
944 Counts the number of times a write CAS command was issued on DRAM channel 0
945 where the command issued used the auto-precharge (auto page close) mode.
948 Counts the number of times a write CAS command was issued on DRAM channel 1.
951 Counts the number of times a write CAS command was issued on DRAM channel 1
952 where the command issued used the auto-precharge (auto page close) mode.
955 Counts the number of times a write CAS command was issued on DRAM channel 2.
958 Counts the number of times a write CAS command was issued on DRAM channel 2
959 where the command issued used the auto-precharge (auto page close) mode.
962 Counts number of DRAM channel 0 refresh commands.
968 Counts number of DRAM channel 1 refresh commands.
973 Counts number of DRAM channel 2 refresh commands.
978 Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close
983 Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close
988 Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close
1009 Cycles that the PCU records that core 3 is above the thermal throttling
1025 Cycles that the PCU records that core 3 is in the power throttled state due
1048 Cycles that the PCU records that core 3 is a low power state due to the
1062 Uncore cycles that core 3 is operating in turbo mode.
1073 .Xr pmc 3 ,
1074 .Xr pmc.amd 3 ,
1075 .Xr pmc.atom 3 ,
1076 .Xr pmc.core 3 ,
1077 .Xr pmc.corei7 3 ,
1078 .Xr pmc.corei7uc 3 ,
1079 .Xr pmc.iaf 3 ,
1080 .Xr pmc.soft 3 ,
1081 .Xr pmc.tsc 3 ,
1082 .Xr pmc.ucf 3 ,
1083 .Xr pmc.westmere 3 ,
1084 .Xr pmc_cpuinfo 3 ,
1085 .Xr pmclog 3 ,