Lines Matching +full:ch0 +full:- +full:2

8 .\" 2. Redistributions in binary form must reproduce the above copyright
40 CPUs contain PMCs conforming to version 2 of the
44 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
59 .%T "Volume 3B: System Programming Guide, Part 2"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
93 Configure the PMC to count the number of de-asserted to asserted
108 .Bl -tag -width indent
199 Cycles GQ Core 0 and 2 input data port is busy importing data from processor
200 cores 0 and 2.
354 Requires writing MSR 301H with mask = 2H
374 Requires writing MSR 301H with mask = 2H
439 .It Li QHL_ADDRESS_CONFLICTS.2WAY
441 Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 conflicts.
472 .It Li QMC_ISOC_FULL.READ.CH0
482 Counts cycles all the entries in the DRAM channel 2 high priority queue are
484 .It Li QMC_ISOC_FULL.WRITE.CH0
494 Counts cycles all the entries in the DRAM channel 2 high priority queue are
496 .It Li QMC_BUSY.READ.CH0
507 read request to DRAM channel 2.
508 .It Li QMC_BUSY.WRITE.CH0
519 write request to DRAM channel 2.
520 .It Li QMC_OCCUPANCY.CH0
521 .Pq Event 2AH , Umask 01H
524 .Pq Event 2AH , Umask 02H
527 .Pq Event 2AH , Umask 04H
528 IMC channel 2 normal read request occupancy.
530 .Pq Event 2AH , Umask 07H
532 .It Li QMC_ISSOC_OCCUPANCY.CH0
533 .Pq Event 2BH , Umask 01H
536 .Pq Event 2BH , Umask 02H
539 .Pq Event 2BH , Umask 04H
540 IMC channel 2 issoc read request occupancy.
542 .Pq Event 2BH , Umask 07H
544 .It Li QMC_NORMAL_READS.CH0
545 .Pq Event 2CH , Umask 01H
551 .Pq Event 2CH , Umask 02H
557 .Pq Event 2CH , Umask 04H
558 Counts the number of Quickpath Memory Controller channel 2 medium and low
560 The QMC channel 2 normal read occupancy divided by this count provides the
561 average QMC channel 2 read latency.
563 .Pq Event 2CH , Umask 07H
567 .It Li QMC_HIGH_PRIORITY_READS.CH0
568 .Pq Event 2DH , Umask 01H
572 .Pq Event 2DH , Umask 02H
576 .Pq Event 2DH , Umask 04H
577 Counts the number of Quickpath Memory Controller channel 2 high priority
580 .Pq Event 2DH , Umask 07H
583 .It Li QMC_CRITICAL_PRIORITY_READS.CH0
584 .Pq Event 2EH , Umask 01H
588 .Pq Event 2EH , Umask 02H
592 .Pq Event 2EH , Umask 04H
593 Counts the number of Quickpath Memory Controller channel 2 critical priority
596 .Pq Event 2EH , Umask 07H
599 .It Li QMC_WRITES.FULL.CH0
600 .Pq Event 2FH , Umask 01H
603 .Pq Event 2FH , Umask 02H
606 .Pq Event 2FH , Umask 04H
607 Counts number of full cache line writes to DRAM channel 2.
609 .Pq Event 2FH , Umask 07H
611 .It Li QMC_WRITES.PARTIAL.CH0
612 .Pq Event 2FH , Umask 08H
615 .Pq Event 2FH , Umask 10H
618 .Pq Event 2FH , Umask 20H
619 Counts number of partial cache line writes to DRAM channel 2.
621 .Pq Event 2FH , Umask 38H
623 .It Li QMC_CANCEL.CH0
631 Counts number of DRAM channel 2 cancel requests.
635 .It Li QMC_PRIORITY_UPDATES.CH0
652 Counts number of DRAM channel 2 priority updates.
664 .It Li IMC_RETRY.CH0
674 Counts number of IMC DRAM channel 2 retries.
762 Counts cycles the Quickpath outbound link 0 non-data response virtual
780 Counts cycles the Quickpath outbound link 1 non-data response virtual
804 Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual
810 Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual
822 Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual
828 Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual
870 .It Li DRAM_OPEN.CH0
880 Counts number of DRAM Channel 2 open commands issued either for read or write.
882 .It Li DRAM_PAGE_CLOSE.CH0
892 DRAM channel 2 command issued to CLOSE a page due to page idle timer expiration.
894 .It Li DRAM_PAGE_MISS.CH0
912 Counts the number of precharges (PRE) that were issued to DRAM channel 2
918 .It Li DRAM_READ_CAS.CH0
924 where the command issued used the auto-precharge (auto page close) mode.
931 where the command issued used the auto-precharge (auto page close) mode.
934 Counts the number of times a read CAS command was issued on DRAM channel 2.
937 Counts the number of times a read CAS command was issued on DRAM channel 2
938 where the command issued used the auto-precharge (auto page close) mode.
939 .It Li DRAM_WRITE_CAS.CH0
945 where the command issued used the auto-precharge (auto page close) mode.
952 where the command issued used the auto-precharge (auto page close) mode.
955 Counts the number of times a write CAS command was issued on DRAM channel 2.
958 Counts the number of times a write CAS command was issued on DRAM channel 2
959 where the command issued used the auto-precharge (auto page close) mode.
960 .It Li DRAM_REFRESH.CH0
973 Counts number of DRAM channel 2 refresh commands.
976 .It Li DRAM_PRE_ALL.CH0
978 Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close
983 Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close
988 Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close
1005 Cycles that the PCU records that core 2 is above the thermal throttling
1021 Cycles that the PCU records that core 2 is in the power throttled state due
1043 Cycles that the PCU records that core 2 is a low power state due to the
1059 Uncore cycles that core 2 is operating in turbo mode.