Lines Matching full:number
52 The number of PMCs available in each class and their widths need to be
60 .%N "Order Number: 253669-033US"
91 Counts the number of demand and DCU prefetch data reads of full
97 Counts the number of demand and DCU prefetch reads for ownership
101 Counts the number of demand and DCU prefetch instruction cacheline
105 Counts the number of writeback (modified to exclusive) transactions.
107 Counts the number of data cacheline reads generated by L2 prefetchers.
109 Counts the number of RFO requests generated by L2 prefetchers.
111 Counts the number of code reads generated by L2 prefetchers.
141 Configure the PMC to increment only if the number of configured
145 Configure the PMC to count the number of de-asserted to asserted
148 condition becomes true, irrespective of the number of clocks during
153 qualifier is present, making the counter increment when the number of
184 Counts number of loads delayed with at-Retirement block code.
201 Counts number of completed page walks due to load miss in the STLB.
207 Number of cache load STLB hits
210 Number of DTLB cache load misses where the low part of the linear to
214 Counts the number of instructions with an architecturally-visible store
219 Counts the number of instructions with an architecturally-visible store
224 Counts the number of instructions exceeding the latency specified with
229 The event counts the number of retired stores that missed the DTLB.
235 Counts the number of Uops issued by the Register Allocation Table to the
240 Counts the number of cycles no Uops issued by the Register Allocation Table
246 Counts the number of fused Uops that were issued from the Register
269 Counts the number of FP Computational Uops Executed.
270 The number of FADD,
277 Counts number of MMX Uops executed.
280 Counts number of SSE and SSE2 FP uops executed.
283 Counts number of SSE2 integer uops executed.
286 Counts number of SSE FP packed uops executed.
289 Counts number of SSE FP scalar uops executed.
292 Counts number of SSE* FP single precision uops executed.
295 Counts number of SSE* FP double precision uops executed.
298 Counts number of 128 bit SIMD integer multiply operations.
301 Counts number of 128 bit SIMD integer shift operations.
304 Counts number of 128 bit SIMD integer pack operations.
307 Counts number of 128 bit SIMD integer unpack operations.
310 Counts number of 128 bit SIMD integer logical operations.
313 Counts number of 128 bit SIMD integer arithmetic operations.
316 Counts number of 128 bit SIMD integer shuffle and move operations.
319 Counts number of loads dispatched from the Reservation Station that bypass
323 Counts the number of delayed RS dispatches at the stage latch.
328 Counts the number of loads dispatched from the Reservation Station to the
335 Counts the number of cycles the divider is busy executing divide or square
339 Set 'edge =1, invert=1, cmask=1' to count the number of divides.
343 Counts the number of multiply operations executed.
349 Counts the number of instructions written into the instruction queue every
353 Counts number of instructions that require decoder 0 to be decoded.
360 This event counts the number of cycles during which instructions are written
362 Dividing this counter by the number of
364 average number of instructions decoded each cycle.
365 If this number is less
373 Number of loops that can not stream from the instruction queue.
376 Counts number of loads that hit the L2 cache.
382 Counts the number of loads that miss the L2 cache.
390 Counts the number of store RFO requests that hit the L2 cache.
397 Counts the number of store RFO requests that miss the L2 cache.
407 Counts number of instruction fetches that hit the L2 cache.
412 Counts number of instruction fetches that miss the L2 cache.
437 Counts number of L2 data demand loads where the cache line to be loaded is
442 Counts number of L2 data demand loads where the cache line to be loaded is
448 Counts number of L2 data demand loads where the cache line to be loaded is
454 Counts number of L2 data demand loads where the cache line to be loaded is
465 Counts number of L2 prefetch data loads where the cache line to be loaded is
469 Counts number of L2 prefetch data loads where the cache line to be loaded is
475 Counts number of L2 prefetch data loads where the cache line to be loaded is
479 Counts number of L2 prefetch data loads where the cache line to be loaded is
489 Counts number of L2 demand store RFO requests where the cache line to be
496 Counts number of L2 store RFO requests where the cache line to be loaded is
502 Counts number of L2 store RFO requests where the cache line to be loaded is
508 Counts number of L2 store RFO requests where the cache line to be loaded is
520 Counts number of L2 demand lock RFO requests where the cache line to be
524 Counts number of L2 lock RFO requests where the cache line to be loaded is
528 Counts number of L2 demand lock RFO requests where the cache line to be
532 Counts number of L2 demand lock RFO requests where the cache line to be
536 Counts number of L2 demand lock RFO requests where the cache line to be
543 Counts number of L1 writebacks to the L2 where the cache line to be written
547 Counts number of L1 writebacks to the L2 where the cache line to be written
551 Counts number of L1 writebacks to the L2 where the cache line to be written
555 Counts number of L1 writebacks to the L2 where the cache line to be written
576 Counts the number of thread cycles while the thread is not in a halt state.
587 Counts the number of misses in the STLB which causes a page walk.
590 Counts number of misses in the STLB which resulted in a completed page walk.
596 Counts the number of DTLB first level misses that hit in the second level
601 Counts number of completed large page walks due to misses in the STLB.
609 Counts number of hardware prefetch requests dispatched out of the prefetch
613 Counts number of hardware prefetch requests that miss the L1D.
623 Counts number of prefetch requests triggered by the Finite State Machine and
634 Counts the number of lines brought into the L1 data cache.
638 Counts the number of modified lines brought into the L1 data cache.
642 Counts the number of modified lines evicted from the L1 data cache due to
647 Counts the number of modified lines evicted from the L1 data cache due to
652 Counts the number of cacheable load lock speculated instructions accepted
656 Counts the number of cacheable load lock speculated or retired instructions
690 Counts the number of cycles that cacheline in the L1 data cache unit is
695 Counts the number of completed I/O transactions.
717 Counts number of large ITLB hits.
720 Counts the number of misses in all levels of the ITLB which causes a page
724 Counts number of misses in all levels of the ITLB which resulted in a
731 Counts number of completed large page walks due to misses in the STLB.
746 Counts the number of regen stalls.
752 Counts the number of conditional near branch instructions executed, but not
760 Counts the number of executed indirect near branch instructions that are not
791 Counts the number of mispredicted conditional near branch instructions
799 Counts the number of executed mispredicted indirect near branch instructions
825 Counts the number of mispredicted near branch instructions that were
829 Counts the number of Allocator resource related stalls.
843 This event counts the number of cycles when the number of instructions in
854 This event counts the number of cycles that a resource related stall will
855 occur due to the number of store instructions reaching the limit of the
864 Counts the number of cycles while execution was stalled due to writing the
873 Counts the number of cycles while execution was stalled due to other
877 Counts the number of instructions decoded that are macro-fused but not
881 Counts number of times a BACLEAR was forced by the Instruction Queue.
893 Counts the number of micro-ops delivered by loop stream detector
897 Counts the number of ITLB flushes
900 Counts number of offcore demand data read requests.
904 Counts number of offcore demand code read requests.
908 Counts number of offcore demand RFO requests.
912 Counts number of offcore read requests.
916 Counts number of offcore RFO requests.
920 Counts number of L1D writebacks to the uncore.
926 Counts number of Uops executed that were issued on port 0.
930 Counts number of Uops executed that were issued on port 1.
935 Counts number of Uops executed that were issued on port 2.
941 Counts number of Uops executed that were issued on port 3.
946 Counts number of Uops executed that where issued on port 4.
951 Counts number of cycles there are one or more uops being executed and were
956 Counts number of Uops executed that where issued on port 5.
959 Counts number of cycles there are one or more uops being executed on any
964 Counts number of Uops executed that where issued on port 0, 1, or 5.
968 Counts number of Uops executed that where issued on port 2, 3, or 4.
971 Counts number of cycles the SQ is full to handle off-core requests.
989 Counts the number of snoop code requests.
992 Counts the number of snoop data requests.
995 Counts the number of snoop invalidate requests
1029 Counts the number of floating point computational operations retired
1035 Counts the number of retired: MMX instructions.
1038 Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
1047 Counts the number of retirement slots used each cycle
1050 Counts number of macro-fused uops retired.
1056 Counts the number of machine clears due to memory order conflicts.
1059 Counts the number of times that a program writes to a code section.
1068 Counts the number of conditional branch instructions retired.
1071 Counts the number of direct & indirect near unconditional calls retired.
1074 Counts the number of branch instructions retired.
1104 Counts the number of retired instructions that missed the ITLB when the
1108 Counts number of retired loads that hit the L1 data cache.
1111 Counts number of retired loads that hit the L2 data cache.
1114 Counts number of retired loads that hit their own, unshared lines in the L3
1118 Counts number of retired loads that hit in a sibling core's L2 (on die
1124 Counts number of retired loads that miss the L3 cache.
1128 Counts number of retired loads that miss the L1D and the address is located
1133 Counts the number of retired loads that missed the DTLB.
1156 Counts the number of instructions decoded, (but not necessarily executed or
1163 Counts the number of Uops decoded by the Microcode Sequencer, MS.
1168 Counts number of stack pointer (ESP) instructions decoded: push , pop , call
1175 Counts number of stack pointer (ESP) sync operations where an ESP
1180 Counts the number of cycles during which execution stalled due to several
1189 This event counts the number of cycles instruction execution latency became
1194 Counts the number of cycles when ROB read port stalls occurred, which did
1220 Counts the number of stall cycles due to the lack of renaming resources for
1227 Counts the number of times the ES segment register is renamed.
1233 Counts the number of branch instructions decoded.
1236 Counts number of times the Branch Prediction Unit missed predicting a call
1240 Counts the number of times the front end is resteered, mainly when the
1250 Counts number of Branch Address Calculator clears (BACLEAR) asserted due to
1295 Counts the number of cache lines allocated in the L2 cache in the S (shared)
1299 Counts the number of cache lines allocated in the L2 cache in the E
1303 Counts the number of cache lines allocated in the L2 cache.
1321 Counts number of Super Queue LRU hints sent to L3.
1324 Counts the number of SQ lock splits across a cache line.
1331 Counts the number of floating point operations executed that required
1340 Counts number of floating point micro-code assist when the output value
1344 Counts number of floating point micro-code assist when the input value (one
1348 Counts number of SID integer 64 bit packed multiply operations.
1351 Counts number of SID integer 64 bit packed shift operations.
1354 Counts number of SID integer 64 bit pack operations.
1357 Counts number of SID integer 64 bit unpack operations.
1360 Counts number of SID integer 64 bit logical operations.
1363 Counts number of SID integer 64 bit arithmetic operations.
1366 Counts number of SID integer 64 bit shift or move operations.