Lines Matching +full:l2 +full:- +full:data +full:- +full:latency

18 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
89 .Bl -tag -width indent
91 Counts the number of demand and DCU prefetch data reads of full
92 and partial cachelines as well as demand data page table entry
94 Does not count L2 data read prefetches or
98 (RFO) requests generated by a write to data cacheline.
99 Does not count L2 RFO.
103 Does not count L2 code read prefetches.
107 Counts the number of data cacheline reads generated by L2 prefetchers.
109 Counts the number of RFO requests generated by L2 prefetchers.
111 Counts the number of code reads generated by L2 prefetchers.
114 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
129 by forwarded data following a cross package snoop where no modified
138 Non-DRAM requests that were serviced by IOH.
145 Configure the PMC to count the number of de-asserted to asserted
172 .Bl -tag -width indent
184 Counts number of loads delayed with at-Retirement block code.
214 Counts the number of instructions with an architecturally-visible store
219 Counts the number of instructions with an architecturally-visible store
224 Counts the number of instructions exceeding the latency specified with
250 Load instructions retired that HIT modified data in sibling core (Precise
254 Load instructions retired local dram and remote cache HIT data sources
258 Load instructions retired with a data source of local DRAM or locally homed
262 Load instructions retired remote DRAM and remote home-remote cache HITM
325 from the one-cycle delayed staging latch before it is written into the LB.
367 decode enough instructions per cycle to sustain the 4-wide pipeline.
376 Counts number of loads that hit the L2 cache.
377 L2 loads include both L1D demand misses as well as L1D prefetches.
378 L2 loads can be rejected for various reasons.
382 Counts the number of loads that miss the L2 cache.
383 L2 loads include both L1D demand misses as well as L1D prefetches.
386 Counts all L2 load requests.
387 L2 loads include both L1D demand misses as well as L1D prefetches.
390 Counts the number of store RFO requests that hit the L2 cache.
391 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO
393 Count includes WC memory requests, where the data is not fetched but the
397 Counts the number of store RFO requests that miss the L2 cache.
398 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO
402 Counts all L2 store RFO requests.
403 L2 RFO requests include both L1D demand
407 Counts number of instruction fetches that hit the L2 cache.
408 L2 instruction fetches include both L1I demand misses as well as L1I
412 Counts number of instruction fetches that miss the L2 cache.
413 L2 instruction fetches include both L1I demand misses as well as L1I
418 L2 instruction fetches include both L1I
422 Counts L2 prefetch hits for both code and data.
425 Counts L2 prefetch misses for both code and data.
428 Counts all L2 prefetches for both code and data.
431 Counts all L2 misses for both code and data.
434 Counts all L2 requests for both code and data.
437 Counts number of L2 data demand loads where the cache line to be loaded is
439 L2 demand loads are both L1D demand misses and L1D prefetches.
442 Counts number of L2 data demand loads where the cache line to be loaded is
444 L2 demand loads are both L1D demand misses and L1D
448 Counts number of L2 data demand loads where the cache line to be loaded is
450 L2 demand loads are both L1D demand misses and
454 Counts number of L2 data demand loads where the cache line to be loaded is
456 L2 demand loads are both L1D demand misses and
460 Counts all L2 data demand requests.
461 L2 demand loads are both L1D demand
465 Counts number of L2 prefetch data loads where the cache line to be loaded is
469 Counts number of L2 prefetch data loads where the cache line to be loaded is
475 Counts number of L2 prefetch data loads where the cache line to be loaded is
479 Counts number of L2 prefetch data loads where the cache line to be loaded is
483 Counts all L2 prefetch requests.
486 Counts all L2 data requests.
489 Counts number of L2 demand store RFO requests where the cache line to be
496 Counts number of L2 store RFO requests where the cache line to be loaded is
502 Counts number of L2 store RFO requests where the cache line to be loaded is
508 Counts number of L2 store RFO requests where the cache line to be loaded is
515 Counts all L2 store RFO requests.The L1D prefetcher does not issue a RFO
520 Counts number of L2 demand lock RFO requests where the cache line to be
524 Counts number of L2 lock RFO requests where the cache line to be loaded is
528 Counts number of L2 demand lock RFO requests where the cache line to be
532 Counts number of L2 demand lock RFO requests where the cache line to be
536 Counts number of L2 demand lock RFO requests where the cache line to be
540 Counts all L2 demand lock RFO requests.
543 Counts number of L1 writebacks to the L2 where the cache line to be written
547 Counts number of L1 writebacks to the L2 where the cache line to be written
551 Counts number of L1 writebacks to the L2 where the cache line to be written
555 Counts number of L1 writebacks to the L2 where the cache line to be written
559 Counts all L1 writebacks to the L2.
564 sizes and other implementation-specific characteristics; value comparison to
566 See Table A-1.
571 and other implementation-specific characteristics; value comparison to
573 See Table A-1.
580 see Table A-1
584 see Table A-1
604 Counts load operations sent to the L1 data cache while a previous SSE
634 Counts the number of lines brought into the L1 data cache.
638 Counts the number of modified lines brought into the L1 data cache.
642 Counts the number of modified lines evicted from the L1 data cache due to
647 Counts the number of modified lines evicted from the L1 data cache due to
660 Counts weighted cycles of offcore demand data read requests.
661 Does not include L2 prefetch requests.
666 Does not include L2 prefetch requests.
671 Does not include L2 prefetch requests.
676 Include L2 prefetch requests.
680 Cycle count during which the L1D and L2 are locked.
686 L1D and L2 locks have a very high performance penalty and
690 Counts the number of cycles that cacheline in the L1 data cache unit is
786 This includes only instructions and not micro-op branches.
810 Counts mispredicted non-indirect near calls executed, (should always be 0).
846 A high count of this event indicates that there are long latency
847 operations in the pipe (possibly load and store operations that miss the L2
858 instruction commits its data to the cache or memory.
861 Counts the cycles of stall due to re- order buffer full.
865 floating-point unit (FPU) control word.
877 Counts the number of instructions decoded that are macro-fused but not
883 direction based on a static scheme and dynamic data provided by the L2
893 Counts the number of micro-ops delivered by loop stream detector
900 Counts number of offcore demand data read requests.
901 Does not count L2 prefetch requests.
905 Does not count L2 prefetch requests.
909 Does not count L2 prefetch requests.
913 Includes L2 prefetch requests.
917 Includes L2 prefetch requests.
952 issued on ports 0-4.
971 Counts number of cycles the SQ is full to handle off-core requests.
972 .It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA
974 Counts weighted cycles of snoopq requests for data.
990 .It Li SNOOPQ_REQUESTS.DATA
992 Counts the number of snoop data requests.
998 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
1015 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
1020 See Table A-1
1031 sub-operations of complex floating point instructions like transcendental
1038 Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
1040 Most instructions are composed of one or two micro-ops.
1050 Counts number of macro-fused uops retired.
1060 Self-modifying code causes a sever penalty in all Intel 64 and IA-32
1062 The modified cache line is written back to the L2 and L3caches.
1065 See Table A-1.
1077 See Table A-1.
1089 Counts SIMD packed single-precision floating point Uops retired.
1092 Counts SIMD calar single-precision floating point Uops retired.
1095 Counts SIMD packed double- precision floating point Uops retired.
1098 Counts SIMD scalar double-precision floating point Uops retired.
1101 Counts 128-bit SIMD vector integer Uops retired.
1108 Counts number of retired loads that hit the L1 data cache.
1111 Counts number of retired loads that hit the L2 data cache.
1118 Counts number of retired loads that hit in a sibling core's L2 (on die
1140 Counts the first floating-point instruction following any MMX instruction.
1142 floating-point and MMX technology states.
1145 Counts the first MMX instruction following a floating-point instruction.
1147 floating-point and MMX technology states.
1153 floating-point and MMX technology states.
1189 This event counts the number of cycles instruction execution latency became
1190 longer than the defined latency because the instruction used a register that
1195 not allow new micro-ops to enter the out-of-order pipeline.
1198 and prevent the stalled micro-ops from entering the pipe.
1200 micro-ops retry entering the execution pipe in the next cycle and the
1201 ROB-read port stall is counted again.
1210 read port stalls occurred, which did not allow new micro-ops to enter the
1213 flag stalls occurred Cycles floating-point unit (FPU) status word stalls
1224 the front- end of the pipeline until the renamed segment retires.
1270 Counts L2 load operations due to HW prefetch or demand loads.
1273 Counts L2 RFO operations due to HW prefetch or demand RFOs.
1276 Counts L2 instruction fetch operations due to HW prefetch or demand ifetch.
1279 Counts L2 prefetch operations.
1282 Counts L1D writeback operations to the L2.
1285 Counts L2 cache line fill operations due to load, RFO, L1D writeback or
1289 Counts L2 writeback operations to the L3.
1292 Counts all L2 cache operations.
1295 Counts the number of cache lines allocated in the L2 cache in the S (shared)
1299 Counts the number of cache lines allocated in the L2 cache in the E
1303 Counts the number of cache lines allocated in the L2 cache.
1306 Counts L2 clean cache lines evicted by a demand request.
1309 Counts L2 dirty (modified) cache lines evicted by a demand request.
1312 Counts L2 clean cache line evicted by a prefetch request.
1315 Counts L2 modified cache line evicted by a prefetch request.
1318 Counts all L2 cache lines evicted for any reason.
1332 micro-code assist intervention.
1340 Counts number of floating point micro-code assist when the output value
1344 Counts number of floating point micro-code assist when the input value (one