Lines Matching +full:data +full:- +full:lines

19 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%N "Order Number: 253669-043US"
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
92 Counts the number of demand and DCU prefetch data reads of full and partial
93 cachelines as well as demand data page table entry cacheline reads.
94 Does not count L2 data read prefetches or instruction fetches.
97 requests generated by a write to data cacheline.
105 Counts the number of data cacheline reads generated by L2 prefetchers.
127 M-state initial lookup stat in L3.
129 E-state.
131 S-state.
133 F-state.
137 No details on snoop-related information.
143 -For LLC Miss, Rspl was returned by all sockets and data was returned from
147 Hit denotes a cache-line was valid before snoop effect.
152 In the LLC Miss case, data is returned from DRAM.
154 A snoop was needed and data was forwarded from a remote socket.
158 A snoop was needed and it HitM-ed in local or remote cache.
159 HitM denotes a cache-line was in modified state before effect as a results of snoop.
165 Target was non-DRAM system address.
173 Configure the PMC to count the number of de-asserted to asserted
200 .Bl -tag -width indent
203 blocked loads due to store buffer blocks with unknown data.
217 Speculative cache-line split load uops dispatched to
221 Speculative cache-line split Store- address uops
282 Counts 256-bit packed single-precision floating-
286 Counts 256-bit packed double-precision floating-
299 Demand Data Read requests that hit L2 cache.
302 Counts any demand and L1 HW prefetch data load
338 ROs that miss cache lines.
341 RFOs that hit cache lines in E state.
344 RFOs that hit cache lines in M state.
347 RFOs that access cache lines in any state.
350 Not rejected writebacks from L1D to L2 cache lines
354 Not rejected writebacks from L1D to L2 cache lines
358 Not rejected writebacks from L1D to L2 cache lines
362 Not rejected writebacks from L1D to L2 cache lines
409 Not SW-prefetch load dispatches that hit fill
413 Not SW-prefetch load dispatches that hit fill
423 Counts the number of lines brought into the
424 L1 data cache.
428 L1D cache lines.
431 Counts the number of modified lines evicted
432 from the L1 data cache due to replacement.
435 Cache lines in M state evicted out of L1D due
439 Increments the number of flags-merge uops in
474 Offcore outstanding Demand Data Read
484 Offcore outstanding cacheable data read
605 Count number of non-delivered uops to RAT per
655 Cycles stalled due to re-order buffer full.
691 DSB Fill encountered > 3 DSB lines.
702 Demand data read requests sent to uncore.
709 Data read requests sent to uncore (demand and
713 Counts total number of uops to be dispatched per-
718 Counts total number of uops to be dispatched per-
733 (Event B7H, Umask 01H) Off-core Response Performance
738 (Event BBH, Umask 01H) Off-core Response Performance
743 DTLB flush attempts of the thread-specific entries.
763 Number of assists associated with 256-bit AVX
767 Number of transitions from AVX-256 to legacy SSE
771 Number of transitions from SSE to AVX-256 when
775 Counts the number of micro-ops retired, Use
895 Retired load uops with L1 cache hits as data
899 Retired load uops with L2 cache hits as data
903 Retired load uops which data sources were data hits
907 Retired load uops which data sources were data
908 missed LLC (excluding unknown data source).
911 Retired load uops which data sources were load
913 the same cache line with data not ready.
916 Retired load uops with unknown information as data
920 Counts the number of times the front end is re-
926 Demand Data Read requests that access L2 cache.
950 L2 cache lines in I state filling L2.
953 L2 cache lines in S state filling L2.
956 L2 cache lines in E state filling L2.
957 .It Li L2_LINES-IN.ALL
959 L2 cache lines filling L2.
962 Clean L2 cache lines evicted by demand.
965 Dirty L2 cache lines evicted by demand.
968 Clean L2 cache lines evicted by L2 prefetch.
971 Dirty L2 cache lines evicted by L2 prefetch.
974 Dirty L2 cache lines filling the L2.
1006 .An -nosplit