Lines Matching +full:full +full:- +full:bridge

32 .Tn Sandy Bridge
40 .Tn "Sandy Bridge"
45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
60 Intel Sandy Bridge PMCs are documented in
62 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
64 .%N "Order Number: 253669-039US"
68 .Ss SANDY BRIDGE FIXED FUNCTION PMCS
71 .Ss SANDY BRIDGE PROGRAMMABLE PMCS
73 .Bl -column "PMC_CAP_INTERRUPT" "Support"
90 .Bl -tag -width indent
92 Configure the Off-core Response bits.
93 .Bl -tag -width indent
95 Counts the number of demand and DCU prefetch data reads of full and partial
130 M-state initial lookup stat in L3.
132 E-state.
134 S-state.
136 F-state.
140 No details on snoop-related information.
150 Hit denotes a cache-line was valid before snoop effect.
161 A snoop was needed and it HitM-ed in local or remote cache.
162 HitM denotes a cache-line was in modified state before effect as a results of snoop.
168 Target was non-DRAM system address.
176 Configure the PMC to count the number of de-asserted to asserted
202 Sandy Bridge programmable PMCs support the following events:
203 .Bl -tag -width indent
218 Speculative cache-line split load uops dispatched to L1D.
221 Speculative cache-line split Store-address uops dispatched to L1D.
273 Counts 256-bit packed single-precision floating-point instructions.
276 Counts 256-bit packed double-precision floating-point instructions.
373 Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
376 Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
382 This accounts for both L1 streamer and IP-based (IPP) HW prefetchers.
399 Increments the number of flags-merge uops in flight each cycle.
412 Cycles stalled due to control structures full for physical registers.
418 Cycles stalled due to out of order resources full.
499 Stall cycles due to IQ is full.
556 Count number of non-delivered uops to RAT per thread.
603 Cycles stalled due to re-order buffer full.
644 Counts total number of uops to be dispatched per-thread each cycle.
648 Counts total number of uops to be dispatched per-core each cycle.
661 Off-core Response Performance Monitoring; PMC0 only.
665 Off-core Response Performance Monitoring.
670 DTLB flush attempts of the thread-specific entries.
694 Number of assists associated with 256-bit AVX store operations.
700 Number of transitions from SSE to AVX-256 when penalty applicable.
703 Counts the number of micro-ops retired.
828 Retired load uops which data sources were LLC hit and cross-core snoop missed in
829 on-pkg core cache.
832 Retired load uops which data sources were LLC and cross-core snoop hits in
833 on-pkg core cache.
879 .It Li L2_LINES-IN.ALL
929 .An -nosplit
934 The support for the Sandy Bridge