Lines Matching +full:data +full:- +full:lines

19 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
62 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
64 .%N "Order Number: 253669-039US"
73 .Bl -column "PMC_CAP_INTERRUPT" "Support"
90 .Bl -tag -width indent
92 Configure the Off-core Response bits.
93 .Bl -tag -width indent
95 Counts the number of demand and DCU prefetch data reads of full and partial
96 cachelines as well as demand data page table entry cacheline reads.
97 Does not count L2 data read prefetches or instruction fetches.
100 requests generated by a write to data cacheline.
108 Counts the number of data cacheline reads generated by L2 prefetchers.
130 M-state initial lookup stat in L3.
132 E-state.
134 S-state.
136 F-state.
140 No details on snoop-related information.
146 -For LLC Miss, Rspl was returned by all sockets and data was returned from
150 Hit denotes a cache-line was valid before snoop effect.
155 In the LLC Miss case, data is returned from DRAM.
157 A snoop was needed and data was forwarded from a remote socket.
161 A snoop was needed and it HitM-ed in local or remote cache.
162 HitM denotes a cache-line was in modified state before effect as a results of snoop.
168 Target was non-DRAM system address.
176 Configure the PMC to count the number of de-asserted to asserted
203 .Bl -tag -width indent
206 Blocked loads due to store buffer blocks with unknown data.
218 Speculative cache-line split load uops dispatched to L1D.
221 Speculative cache-line split Store-address uops dispatched to L1D.
273 Counts 256-bit packed single-precision floating-point instructions.
276 Counts 256-bit packed double-precision floating-point instructions.
286 Demand Data Read requests that hit L2 cache.
289 Counts any demand and L1 HW prefetch data load requests to L2.
319 RFOs that miss cache lines.
322 RFOs that hit cache lines in E state.
325 RFOs that hit cache lines in M state.
328 RFOs that access cache lines in any state.
331 Not rejected writebacks from L1D to L2 cache lines in E state.
334 Not rejected writebacks from L1D to L2 cache lines in M state.
373 Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
376 Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
382 This accounts for both L1 streamer and IP-based (IPP) HW prefetchers.
385 Counts the number of lines brought into the L1 data cache.
388 Counts the number of allocations of modified L1D cache lines.
391 Counts the number of modified lines evicted from the L1 data cache due to
395 Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line
399 Increments the number of flags-merge uops in flight each cycle.
431 Offcore outstanding Demand Data Read transactions in SQ to uncore.
439 Offcore outstanding cacheable data read transactions in SQ to uncore.
556 Count number of non-delivered uops to RAT per thread.
603 Cycles stalled due to re-order buffer full.
625 DSB Fill encountered > 3 DSB lines.
635 Demand data read requests sent to uncore.
641 Data read requests sent to uncore (demand and prefetch).
644 Counts total number of uops to be dispatched per-thread each cycle.
648 Counts total number of uops to be dispatched per-core each cycle.
661 Off-core Response Performance Monitoring; PMC0 only.
665 Off-core Response Performance Monitoring.
670 DTLB flush attempts of the thread-specific entries.
694 Number of assists associated with 256-bit AVX store operations.
700 Number of transitions from SSE to AVX-256 when penalty applicable.
703 Counts the number of micro-ops retired.
813 Retired load uops with L1 cache hits as data sources.
817 Retired load uops with L2 cache hits as data sources.
820 Retired load uops which data sources were data hits in LLC without snoops
824 Retired load uops which data sources were load uops missed L1 but hit FB due
825 to preceding miss to the same cache line with data not ready.
828 Retired load uops which data sources were LLC hit and cross-core snoop missed in
829 on-pkg core cache.
832 Retired load uops which data sources were LLC and cross-core snoop hits in
833 on-pkg core cache.
836 Retired load uops which data sources were HitM responses from shared LLC.
839 Retired load uops which data sources were hits in LLC without snoops required.
842 Retired load uops with unknown information as data source in cache serviced the load.
845 Demand Data Read requests that access L2 cache.
869 L2 cache lines in I state filling L2.
873 L2 cache lines in S state filling L2.
877 L2 cache lines in E state filling L2.
879 .It Li L2_LINES-IN.ALL
881 L2 cache lines filling L2.
885 Clean L2 cache lines evicted by demand.
888 Dirty L2 cache lines evicted by demand.
891 Clean L2 cache lines evicted by L2 prefetch.
894 Dirty L2 cache lines evicted by L2 prefetch.
897 Dirty L2 cache lines filling the L2.
929 .An -nosplit