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19 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
60 .%N "Order Number: 325462-045US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
89 .Bl -tag -width indent
91 Counts the number of demand and DCU prefetch data reads of full and partial
92 cachelines as well as demand data page table entry cacheline reads.
93 Does not count L2 data read prefetches or instruction fetches.
96 requests generated by a write to data cacheline.
104 Counts the number of data cacheline reads generated by L2 prefetchers.
126 M-state initial lookup stat in L3.
128 E-state.
130 S-state.
132 F-state.
136 No details on snoop-related information.
142 -For LLC Miss, Rspl was returned by all sockets and data was returned from
146 Hit denotes a cache-line was valid before snoop effect.
151 In the LLC Miss case, data is returned from DRAM.
153 A snoop was needed and data was forwarded from a remote socket.
157 A snoop was needed and it HitM-ed in local or remote cache.
158 HitM denotes a cache-line was in modified state before effect as a results of snoop.
164 Target was non-DRAM system address.
172 Configure the PMC to count the number of de-asserted to asserted
199 .Bl -tag -width indent
205 Speculative cache-line split load uops dispatched to L1D.
208 Speculative cache-line split Store- address uops dispatched to L1D.
228 Number of flags-merge uops allocated.
243 Demand Data Read requests that hit L2 cache.
246 Counts any demand and L1 HW prefetch data load requests to L2.
276 RFOs that miss cache lines.
279 RFOs that hit cache lines in M state.
282 RFOs that access cache lines in any state.
288 Not rejected writebacks from L1D to L2 cache lines in E state.
291 Not rejected writebacks from L1D to L2 cache lines in M state.
294 Not rejected writebacks from L1D to L2 cache lines in any state.
333 Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
336 Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
339 Counts the number of lines brought into the L1 data cache.
367 Offcore outstanding Demand Data Read transactions in SQ to uncore.
379 Offcore outstanding cacheable data read transactions in SQ to uncore.
515 Count number of non-delivered uops to RAT per thread.
559 Cycles stalled due to re-order buffer full.
584 DSB Fill encountered > 3 DSB lines.
590 Demand data read requests sent to uncore.
600 Data read requests sent to uncore (demand and prefetch).
603 Counts total number of uops to be executed per-thread each cycle.
607 Counts total number of uops to be executed per-core each cycle.
611 Off-core Response Performance Monitoring.
616 Off-core Response Performance Monitoring.
621 DTLB flush attempts of the thread- specific entries.
636 Number of assists associated with 256-bit AVX store operations.
639 Number of transitions from AVX- 256 to legacy SSE when penalty applicable.
642 Number of transitions from SSE to AVX-256 when penalty applicable.
645 Counts the number of micro-ops retired, Use cmask=1 and invert to count
656 Number of self-modifying-code machine clears detected.
752 Retired load uops with L1 cache hits as data sources.
756 Retired load uops with L2 cache hits as data sources.
759 Retired load uops whose data source was LLC hit with no snoop required.
762 Retired load uops whose data source is LLC miss.
765 Retired load uops which data sources were load uops missed L1 but hit FB due
766 to preceding miss to the same cache line with data not ready.
769 Retired load uops which data sources were LLC hit and cross-core snoop
770 missed in on-pkg core cache.
774 Retired load uops which data sources were LLC and cross-core snoop hits in
775 on-pkg core cache.
779 Retired load uops which data sources were HitM responses from shared LLC.
782 Retired load uops which data sources were hits in LLC without snoops
786 Retired load uops which data sources missed LLC but serviced from local
791 Retired load uops whose data source was remote DRAM.
794 Retired load uops whose data source was remote HITM.
797 Retired load uops whose data source was forwards from a remote cache.
800 Number of front end re-steers due to BPU misprediction.
803 Demand Data Read requests that access L2 cache.
827 L2 cache lines in I state filling L2.
831 L2 cache lines in S state filling L2.
835 L2 cache lines in E state filling L2.
839 L2 cache lines filling L2.
843 Clean L2 cache lines evicted by demand.
846 Dirty L2 cache lines evicted by demand.
849 Clean L2 cache lines evicted by the MLC prefetcher.
852 Dirty L2 cache lines evicted by the MLC prefetcher.
855 Dirty L2 cache lines filling the L2.
883 .An -nosplit