Lines Matching full:loads

113 L2 prefetcher to L3 for loads.
205 Loads blocked by overlapping with store buffer that
207 .It Li MISALIGN_MEM_REF.LOADS
646 Cycles with pending L2 miss loads.
650 Cycles with pending memory loads.
654 Number of loads missed L2.
657 Cycles with pending L1 cache miss loads.
688 Number of DTLB page walker loads that hit in the
692 Number of ITLB page walker loads that hit in the
696 Number of DTLB page walker loads that hit in the L2.
699 Number of ITLB page walker loads that hit in the L2.
702 Number of DTLB page walker loads that hit in the L3.
705 Number of ITLB page walker loads that hit in the L3.
708 Number of DTLB page walker loads from memory.
711 Number of ITLB page walker loads from memory.
815 Randomly sampled loads whose latency is above a
817 A small fraction of the overall loads are sampled due to randomization.