Lines Matching +full:l2 +full:- +full:cache

46 .Bl -tag -width "Li PMC_CLASS_IAP"
48 Fixed-function counters that count only one hardware event per counter.
60 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
62 .%N "Order Number: 325462-052US"
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
88 .Bl -tag -width indent
90 Configure the Off-core Response bits.
91 .Bl -tag -width indent
96 Does not count L2 data read prefetches or instruction fetches.
100 Does not count L2 RFO prefetches.
103 Does not count L2 code read prefetches.
107 Counts the number of data cacheline reads generated by L2 prefetchers.
109 Counts the number of RFO requests generated by L2 prefetchers.
111 Counts the number of code reads generated by L2 prefetchers.
113 L2 prefetcher to L3 for loads.
115 RFO requests generated by L2 prefetcher
117 L2 prefetcher to L3 for instruction fetches.
129 M-state initial lookup stat in L3.
131 E-state.
133 S-state.
135 F-state.
139 No details on snoop-related information.
148 A snoop was needed and it hits in at least one snooped cache.
149 Hit denotes a cache-line was valid before snoop effect.
160 A snoop was needed and it HitM-ed in local or remote cache.
161 HitM denotes a cache-line was in modified state before effect as a results of snoop.
167 Target was non-DRAM system address.
175 Configure the PMC to count the number of de-asserted to asserted
202 .Bl -tag -width indent
209 Speculative cache-line split load uops dispatched to
213 Speculative cache-line split Store-address uops
246 Number of cache load STLB hits.
250 DTLB demand load misses with low part of linear-to-
265 Number of flags-merge uops allocated.
278 Demand Data Read requests that missed L2, no
282 Demand Data Read requests that hit L2 cache.
286 requests to L2.
290 the L2 cache.
294 the L2 cache.
297 Counts all L2 store RFO requests.
300 Number of instruction fetches that hit the L2 cache.
303 Number of instruction fetches that missed the L2
304 cache.
307 Demand requests that miss L2 cache.
310 Demand requests to L2 cache.
313 Counts all L2 code requests.
316 Counts all L2 HW prefetcher requests that hit L2.
319 Counts all L2 HW prefetcher requests that missed
320 L2.
323 Counts all L2 HW prefetcher requests.
326 All requests that missed L2.
329 All requests to L2 cache.
332 Not rejected writebacks that hit L2 cache
336 that reference a cache line in the last level cache.
339 This event counts each cache miss condition for
340 references to the last level cache.
388 DTLB store misses with low part of linear-to-physical
392 Non-SW-prefetch load dispatches that hit fill buffer
396 Non-SW-prefetch load dispatches that hit fill buffer
401 cache.
447 Cycles in which the L1D and L2 are locked, due to a
502 Number of Instruction Cache, Streaming Buffer and
503 Victim Cache Misses.
596 Count number of non-delivered uops to RAT per
643 Cycles stalled due to re-order buffer full.
646 Cycles with pending L2 miss loads.
654 Number of loads missed L2.
657 Cycles with pending L1 cache miss loads.
678 Counts total number of uops to be executed per-core
696 Number of DTLB page walker loads that hit in the L2.
699 Number of ITLB page walker loads that hit in the L2.
714 DTLB flush attempts of the thread-specific entries.
727 Number of transitions from AVX-256 to legacy SSE
731 Number of transitions from SSE to AVX-256 when
739 Counts the number of micro-ops retired, Use
752 Number of self-modifying-code machine clears
826 Count retired load uops that were split across a cache line.
829 Count retired store uops that were split across a cache line.
838 Retired load uops with L1 cache hits as data sources.
841 Retired load uops with L2 cache hits as data sources.
844 Retired load uops with LLC cache hits as data
848 Retired load uops missed L2.
854 same cache line with data not ready.
858 and cross-core snoop missed in on-pkg core cache.
862 cross-core snoop hits in on-pkg core cache.
877 Number of front end re-steers due to BPU
881 Demand Data Read requests that access L2 cache.
884 RFO requests that access L2 cache.
887 L2 cache accesses when fetching instructions.
890 Any MLC or LLC HW prefetch accessing L2, including
894 L1D writebacks that access L2 cache.
897 L2 fill requests that access L2 cache.
900 L2 writebacks that access L2 cache.
903 Transactions accessing L2 pipe.
906 L2 cache lines in I state filling L2.
909 L2 cache lines in S state filling L2.
912 L2 cache lines in E state filling L2.
915 L2 cache lines filling L2.
918 Clean L2 cache lines evicted by demand.
921 Dirty L2 cache lines evicted by demand.