Lines Matching +full:store +full:- +full:conditional

45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%N "Order Number: 325462-045US"
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
120 Streaming store requests.
128 M-state initial lookup stat in L3.
130 E-state.
132 S-state.
134 F-state.
138 No details on snoop-related information.
148 Hit denotes a cache-line was valid before snoop effect.
159 A snoop was needed and it HitM-ed in local or remote cache.
160 HitM denotes a cache-line was in modified state before effect as a results of snoop.
166 Target was non-DRAM system address.
174 Configure the PMC to count the number of de-asserted to asserted
201 .Bl -tag -width indent
204 Loads blocked by overlapping with store buffer that
208 Speculative cache-line split load uops dispatched to
212 Speculative cache-line split Store-address uops
249 DTLB demand load misses with low part of linear-to-
264 Number of flags-merge uops allocated.
288 Counts the number of store RFO requests that hit
292 Counts the number of store RFO requests that miss
296 Counts all L2 store RFO requests.
359 Completed page walks due to store misses in one or
363 Completed page walks due to store misses in one or
367 Completed page walks due to store miss in any TLB
374 Store misses that missed DTLB but hit STLB (4K).
377 Store misses that missed DTLB but hit STLB (2M).
380 Store operations that miss the first TLB level but hit
384 DTLB store misses with low part of linear-to-physical
388 Non-SW-prefetch load dispatches that hit fill buffer
392 Non-SW-prefetch load dispatches that hit fill buffer
432 Offcore outstanding RFO store transactions in SQ to uncore.
529 Count conditional near branch instructions that were executed (but not
533 Count conditional near branch instructions that were executed (but not
559 Count conditional near branch instructions mispredicted as nontaken.
562 Count conditional near branch instructions mispredicted as taken.
583 Count number of non-delivered uops to RAT per
626 Cycles stalled due to no store buffers available (not
630 Cycles stalled due to re-order buffer full.
666 Counts total number of uops to be executed per-core
702 DTLB flush attempts of the thread-specific entries.
715 Number of transitions from AVX-256 to legacy SSE
719 Number of transitions from SSE to AVX-256 when
727 Counts the number of micro-ops retired, Use
740 Number of self-modifying-code machine clears
750 .It Li BR_INST_RETIRED.CONDITIONAL
752 Counts the number of conditional branch instructions Supports PEBS
777 .It Li BR_MISP_RETIRED.CONDITIONAL
779 Mispredicted conditional branch instructions retired.
780 .It Li BR_MISP_RETIRED.CONDITIONAL
810 Count retired store uops that missed the STLB.
816 Count retired store uops that were split across a cache line.
822 Count all retired store uops.
845 and cross-core snoop missed in on-pkg core cache.
849 cross-core snoop hits in on-pkg core cache.
864 Number of front end re-steers due to BPU
938 .An -nosplit