Lines Matching +full:write +full:- +full:data

18 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
44 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
92 Configure the PMC to count the number of de-asserted to asserted
107 .Bl -tag -width indent
113 Uncore cycles Global Queue write tracker is full.
123 Uncore cycles were Global Queue write tracker has at least one valid entry.
160 Counts the number of GQ write tracker entries that are allocated in the
161 write tracker, have missed in the L3 and have not acquired a Request
163 The GQ write tracker L3 miss to RTID occupancy count is divided by this count
164 to obtain the average latency for a write L3 miss to acquire an RTID.
167 Counts the number of GQ write tracker entries that are allocated in the
168 write tracker queue that miss the L3.
169 The GQ write tracker occupancy count is divided by the this count to obtain the average L3 write mi…
178 Cycles Global Queue Quickpath Interface input data port is busy importing
179 data from the Quickpath Interface.
180 Each cycle the input port can transfer 8 or 16 bytes of data.
183 Cycles Global Queue Quickpath Memory Interface input data port is busy
184 importing data from the Quickpath Memory Interface.
185 Each cycle the input port can transfer 8 or 16 bytes of data.
188 Cycles GQ L3 input data port is busy importing data from the Last Level Cache.
189 Each cycle the input port can transfer 32 bytes of data.
192 Cycles GQ Core 0 and 2 input data port is busy importing data from processor
194 Each cycle the input port can transfer 32 bytes of data.
197 Cycles GQ Core 1 and 3 input data port is busy importing data from processor
199 Each cycle the input port can transfer 32 bytes of data.
202 Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath
204 Each cycle the output port can transfer 32 bytes of data.
207 Cycles GQ L3 output data port is busy sending data to the Last Level Cache.
208 Each cycle the output port can transfer 32 bytes of data.
211 Cycles GQ Core output data port is busy sending data to the Cores.
212 Each cycle the output port can transfer 32 bytes of data.
223 Number of responses to code or data read snoops to the local home that the
238 Number of responses to code or data read snoops to the local home that the
250 Number of responses to code or data read snoops to a remote home that the L3
265 Number of responses to code or data read snoops to a remote home that the L3
272 Number of code read, data read and RFO requests that hit in the L3
273 .It Li L3_HITS.WRITE
285 Number of code read, data read and RFO requests that miss the L3.
286 .It Li L3_MISS.WRITE
339 Counts number of Quickpath Home Logic write requests from the IOH.
345 Counts number of Quickpath Home Logic write requests from a remote socket.
351 Counts number of Quickpath Home Logic write requests from the local socket.
430 .It Li QMC_NORMAL_FULL.WRITE.CH0
433 queue are occupied with write requests.
434 .It Li QMC_NORMAL_FULL.WRITE.CH1
437 queue are occupied with write requests.
438 .It Li QMC_NORMAL_FULL.WRITE.CH2
441 queue are occupied with write requests.
454 .It Li QMC_ISOC_FULL.WRITE.CH0
457 occupied with isochronous write requests.
458 .It Li QMC_ISOC_FULL.WRITE.CH1
461 occupied with isochronous write requests.
462 .It Li QMC_ISOC_FULL.WRITE.CH2
465 occupied with isochronous write requests.
478 .It Li QMC_BUSY.WRITE.CH0
481 write request to DRAM channel 0.
482 .It Li QMC_BUSY.WRITE.CH1
485 write request to DRAM channel 1.
486 .It Li QMC_BUSY.WRITE.CH2
489 write request to DRAM channel 2.
649 Counts cycles the Quickpath outbound link 0 non-data response virtual
667 Counts cycles the Quickpath outbound link 1 non-data response virtual
685 Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is
691 Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual
697 Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual
703 Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is
709 Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual
715 Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual
751 Counts number of DRAM Channel 0 open commands issued either for read or write.
752 To read or write data, the referenced DRAM page must first be opened.
755 Counts number of DRAM Channel 1 open commands issued either for read or write.
756 To read or write data, the referenced DRAM page must first be opened.
759 Counts number of DRAM Channel 2 open commands issued either for read or write.
760 To read or write data, the referenced DRAM page must first be opened.
806 where the command issued used the auto-precharge (auto page close) mode.
813 where the command issued used the auto-precharge (auto page close) mode.
820 where the command issued used the auto-precharge (auto page close) mode.
823 Counts the number of times a write CAS command was issued on DRAM channel 0.
826 Counts the number of times a write CAS command was issued on DRAM channel 0
827 where the command issued used the auto-precharge (auto page close) mode.
830 Counts the number of times a write CAS command was issued on DRAM channel 1.
833 Counts the number of times a write CAS command was issued on DRAM channel 1
834 where the command issued used the auto-precharge (auto page close) mode.
837 Counts the number of times a write CAS command was issued on DRAM channel 2.
840 Counts the number of times a write CAS command was issued on DRAM channel 2
841 where the command issued used the auto-precharge (auto page close) mode.
845 DRAM loses data content over time.
846 In order to keep correct data content, the data values have to be
851 DRAM loses data content over time.
852 In order to keep correct data content, the data values have to be
857 DRAM loses data content over time.
858 In order to keep correct data content, the data values have to be
862 Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close
868 Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close
874 Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close