Lines Matching +full:channel +full:- +full:3

44 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
54 .Xr pmc_cpuinfo 3 .
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
59 .%T "Volume 3B: System Programming Guide, Part 2"
60 .%N "Order Number: 253669-033US"
66 .Xr pmc.ucf 3 .
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
92 Configure the PMC to count the number of de-asserted to asserted
107 .Bl -tag -width indent
197 Cycles GQ Core 1 and 3 input data port is busy importing data from processor
198 cores 1 and 3.
390 .It Li QHL_ADDRESS_CONFLICTS.3WAY
392 Counts number of QHL Active Address Table (AAT) entries that saw a max of 3
401 A max of 3 requests can be in conflict.
406 A max of 3 requests can be in conflict.
411 A max of 3 requests can be in conflict.
420 Uncore cycles all the entries in the DRAM channel 0 medium or low priority
424 Uncore cycles all the entries in the DRAM channel 1 medium or low priority
428 Uncore cycles all the entries in the DRAM channel 2 medium or low priority
432 Uncore cycles all the entries in the DRAM channel 0 medium or low priority
436 Counts cycles all the entries in the DRAM channel 1 medium or low priority
440 Uncore cycles all the entries in the DRAM channel 2 medium or low priority
444 Counts cycles all the entries in the DRAM channel 0 high priority queue are
448 Counts cycles all the entries in the DRAM channel 1 high priority queue are
452 Counts cycles all the entries in the DRAM channel 2 high priority queue are
456 Counts cycles all the entries in the DRAM channel 0 high priority queue are
460 Counts cycles all the entries in the DRAM channel 1 high priority queue are
464 Counts cycles all the entries in the DRAM channel 2 high priority queue are
469 read request to DRAM channel 0.
473 read request to DRAM channel 1.
477 read request to DRAM channel 2.
481 write request to DRAM channel 0.
485 write request to DRAM channel 1.
489 write request to DRAM channel 2.
492 IMC channel 0 normal read request occupancy.
495 IMC channel 1 normal read request occupancy.
498 IMC channel 2 normal read request occupancy.
501 IMC channel 0 issoc read request occupancy.
504 IMC channel 1 issoc read request occupancy.
507 IMC channel 2 issoc read request occupancy.
513 Counts the number of Quickpath Memory Controller channel 0 medium and low
515 The QMC channel 0 normal read occupancy divided by this count provides the
516 average QMC channel 0 read latency.
519 Counts the number of Quickpath Memory Controller channel 1 medium and low
521 The QMC channel 1 normal read occupancy divided by this count provides the
522 average QMC channel 1 read latency.
525 Counts the number of Quickpath Memory Controller channel 2 medium and low
527 The QMC channel 2 normal read occupancy divided by this count provides the
528 average QMC channel 2 read latency.
537 Counts the number of Quickpath Memory Controller channel 0 high priority
541 Counts the number of Quickpath Memory Controller channel 1 high priority
545 Counts the number of Quickpath Memory Controller channel 2 high priority
553 Counts the number of Quickpath Memory Controller channel 0 critical priority
557 Counts the number of Quickpath Memory Controller channel 1 critical priority
561 Counts the number of Quickpath Memory Controller channel 2 critical priority
569 Counts number of full cache line writes to DRAM channel 0.
572 Counts number of full cache line writes to DRAM channel 1.
575 Counts number of full cache line writes to DRAM channel 2.
581 Counts number of partial cache line writes to DRAM channel 0.
584 Counts number of partial cache line writes to DRAM channel 1.
587 Counts number of partial cache line writes to DRAM channel 2.
593 Counts number of DRAM channel 0 cancel requests.
596 Counts number of DRAM channel 1 cancel requests.
599 Counts number of DRAM channel 2 cancel requests.
605 Counts number of DRAM channel 0 priority updates.
612 Counts number of DRAM channel 1 priority updates.
619 Counts number of DRAM channel 2 priority updates.
637 Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled
640 selected for arbitration because another virtual channel is getting arbitrated.
643 Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled
646 selected for arbitration because another virtual channel is getting arbitrated.
649 Counts cycles the Quickpath outbound link 0 non-data response virtual
650 channel is stalled due to lack of a VNA and VN0 credit.
652 selected for arbitration because another virtual channel is getting arbitrated.
655 Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled
658 selected for arbitration because another virtual channel is getting arbitrated.
661 Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled
664 selected for arbitration because another virtual channel is getting arbitrated.
667 Counts cycles the Quickpath outbound link 1 non-data response virtual
668 channel is stalled due to lack of a VNA and VN0 credit.
670 selected for arbitration because another virtual channel is getting arbitrated.
676 selected for arbitration because another virtual channel is getting arbitrated.
682 selected for arbitration because another virtual channel is getting arbitrated.
685 Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is
688 selected for arbitration because another virtual channel is getting arbitrated.
691 Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual
692 channel is stalled due to lack of VNA and VN0 credits.
694 selected for arbitration because another virtual channel is getting arbitrated.
697 Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual
698 channel is stalled due to lack of VNA and VN0 credits.
700 selected for arbitration because another virtual channel is getting arbitrated.
703 Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is
706 selected for arbitration because another virtual channel is getting arbitrated.
709 Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual
710 channel is stalled due to lack of VNA and VN0 credits.
712 selected for arbitration because another virtual channel is getting arbitrated.
715 Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual
716 channel is stalled due to lack of VNA and VN0 credits.
718 selected for arbitration because another virtual channel is getting arbitrated.
724 selected for arbitration because another virtual channel is getting arbitrated.
730 selected for arbitration because another virtual channel is getting arbitrated.
751 Counts number of DRAM Channel 0 open commands issued either for read or write.
755 Counts number of DRAM Channel 1 open commands issued either for read or write.
759 Counts number of DRAM Channel 2 open commands issued either for read or write.
763 DRAM channel 0 command issued to CLOSE a page due to page idle timer
768 DRAM channel 1 command issued to CLOSE a page due to page idle timer
773 DRAM channel 2 command issued to CLOSE a page due to page idle timer
778 Counts the number of precharges (PRE) that were issued to DRAM channel 0
786 Counts the number of precharges (PRE) that were issued to DRAM channel 1
794 Counts the number of precharges (PRE) that were issued to DRAM channel 2
802 Counts the number of times a read CAS command was issued on DRAM channel 0.
805 Counts the number of times a read CAS command was issued on DRAM channel 0
806 where the command issued used the auto-precharge (auto page close) mode.
809 Counts the number of times a read CAS command was issued on DRAM channel 1.
812 Counts the number of times a read CAS command was issued on DRAM channel 1
813 where the command issued used the auto-precharge (auto page close) mode.
816 Counts the number of times a read CAS command was issued on DRAM channel 2.
819 Counts the number of times a read CAS command was issued on DRAM channel 2
820 where the command issued used the auto-precharge (auto page close) mode.
823 Counts the number of times a write CAS command was issued on DRAM channel 0.
826 Counts the number of times a write CAS command was issued on DRAM channel 0
827 where the command issued used the auto-precharge (auto page close) mode.
830 Counts the number of times a write CAS command was issued on DRAM channel 1.
833 Counts the number of times a write CAS command was issued on DRAM channel 1
834 where the command issued used the auto-precharge (auto page close) mode.
837 Counts the number of times a write CAS command was issued on DRAM channel 2.
840 Counts the number of times a write CAS command was issued on DRAM channel 2
841 where the command issued used the auto-precharge (auto page close) mode.
844 Counts number of DRAM channel 0 refresh commands.
850 Counts number of DRAM channel 1 refresh commands.
856 Counts number of DRAM channel 2 refresh commands.
862 Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close
868 Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close
874 Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close
880 .Xr pmc 3 ,
881 .Xr pmc.amd 3 ,
882 .Xr pmc.atom 3 ,
883 .Xr pmc.core 3 ,
884 .Xr pmc.corei7 3 ,
885 .Xr pmc.iaf 3 ,
886 .Xr pmc.soft 3 ,
887 .Xr pmc.tsc 3 ,
888 .Xr pmc.ucf 3 ,
889 .Xr pmc.westmere 3 ,
890 .Xr pmc.westmereuc 3 ,
891 .Xr pmc_cpuinfo 3 ,
892 .Xr pmclog 3 ,