Lines Matching +full:read +full:- +full:to +full:- +full:read

13 .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
40 CPUs contain PMCs conforming to version 2 of the
44 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
52 The number of PMCs available in each class and their widths need to be
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the PMC to increment only if the number of configured
89 events measured in a cycle is greater than or equal to
92 Configure the PMC to count the number of de-asserted to asserted
107 .Bl -tag -width indent
110 Uncore cycles Global Queue read tracker is full.
120 Uncore cycles were Global Queue read tracker has at least one valid entry.
130 Counts the number of tread tracker allocate to deallocate entries.
131 The GQ read tracker allocate to deallocate occupancy count is divided
132 by the count to obtain the average read tracker latency.
135 Counts the number GQ read tracker entries for which a full cache line read
137 The GQ read tracker L3 miss to fill occupancy count is divided by this count
138 to obtain the average cache line read L3 miss latency.
141 The time between a GQ read tracker allocation and the L3 determining that the
143 The total L3 cache line read miss latency is the hit latency + L3 miss
147 Counts the number of GQ read tracker entries that are allocated in the read
149 The GQ read tracker L3 hit occupancy count is divided by this count to obtain
153 Counts the number of GQ read tracker entries that are allocated in the read
155 The GQ read tracker L3 miss to RTID acquired occupancy count is
156 divided by this count to obtain the average latency for a read L3 miss to
163 The GQ write tracker L3 miss to RTID occupancy count is divided by this count
164 to obtain the average latency for a write L3 miss to acquire an RTID.
169 The GQ write tracker occupancy count is divided by the this count to obtain the average L3 write mi…
174 The GQ peer probe occupancy count is divided by this count to obtain the average L3 peer
202 Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath
207 Cycles GQ L3 output data port is busy sending data to the Last Level Cache.
211 Cycles GQ Core output data port is busy sending data to the Cores.
215 Number of snoop responses to the local home that L3 does not have the
219 Number of snoop responses to the local home that L3 has the referenced line
223 Number of responses to code or data read snoops to the local home that the
225 The L3 cache line state is changed to the S state and the line is
226 forwarded to the local home in the S state.
229 Number of responses to read invalidate snoops to the local home that the L3
231 The L3 cache line state is invalidated and the line is forwarded to the
235 Number of conflict snoop responses sent to the local home.
238 Number of responses to code or data read snoops to the local home that the
242 Number of snoop responses to a remote home that L3 does not have the
246 Number of snoop responses to a remote home that L3 has the referenced line
250 Number of responses to code or data read snoops to a remote home that the L3
252 The L3 cache line state is changed to the S state and the line is forwarded to
256 Number of responses to read invalidate snoops to a remote home that the L3
258 The L3 cache line state is invalidated and the line is forwarded to the
262 Number of conflict snoop responses sent to the local home.
265 Number of responses to code or data read snoops to a remote home that the L3
269 Number of HITM snoop responses to a remote home
270 .It Li L3_HITS.READ
272 Number of code read, data read and RFO requests that hit in the L3
276 Writebacks from the cores will always result in L3 hits due to the inclusive property of the L3.
283 .It Li L3_MISS.READ
285 Number of code read, data read and RFO requests that miss the L3.
290 L3 hits due to the inclusive property of the L3.
301 was forwarded in M state is forwarded due to a Snoop Read Invalidate Own request.
317 When the victim cache line is in M state, the line is written to its home cache agent
336 Counts number of Quickpath Home Logic read requests from the IOH.
342 Counts number of Quickpath Home Logic read requests from a remote socket.
348 Counts number of Quickpath Home Logic read requests from the local socket.
376 QHL IOH tracker allocate to deallocate read occupancy.
379 QHL remote tracker allocate to deallocate read occupancy.
382 QHL local tracker allocate to deallocate read occupancy.
414 Counts number or requests to the Quickpath Memory Controller that bypass the
417 For remote requests, only read requests can be bypassed.
418 .It Li QMC_NORMAL_FULL.READ.CH0
421 queue are occupied with read requests.
422 .It Li QMC_NORMAL_FULL.READ.CH1
425 queue are occupied with read requests.
426 .It Li QMC_NORMAL_FULL.READ.CH2
429 queue are occupied with read requests.
442 .It Li QMC_ISOC_FULL.READ.CH0
445 occupied with isochronous read requests.
446 .It Li QMC_ISOC_FULL.READ.CH1
449 occupied with isochronous read requests.
450 .It Li QMC_ISOC_FULL.READ.CH2
453 occupied with isochronous read requests.
466 .It Li QMC_BUSY.READ.CH0
469 read request to DRAM channel 0.
470 .It Li QMC_BUSY.READ.CH1
473 read request to DRAM channel 1.
474 .It Li QMC_BUSY.READ.CH2
477 read request to DRAM channel 2.
481 write request to DRAM channel 0.
485 write request to DRAM channel 1.
489 write request to DRAM channel 2.
492 IMC channel 0 normal read request occupancy.
495 IMC channel 1 normal read request occupancy.
498 IMC channel 2 normal read request occupancy.
501 IMC channel 0 issoc read request occupancy.
504 IMC channel 1 issoc read request occupancy.
507 IMC channel 2 issoc read request occupancy.
510 IMC issoc read request occupancy.
514 priority read requests.
515 The QMC channel 0 normal read occupancy divided by this count provides the
516 average QMC channel 0 read latency.
520 priority read requests.
521 The QMC channel 1 normal read occupancy divided by this count provides the
522 average QMC channel 1 read latency.
526 priority read requests.
527 The QMC channel 2 normal read occupancy divided by this count provides the
528 average QMC channel 2 read latency.
532 read requests.
533 The QMC normal read occupancy divided by this count provides the average
534 QMC read latency.
538 isochronous read requests.
542 isochronous read requests.
546 isochronous read requests.
550 read requests.
554 isochronous read requests.
558 isochronous read requests.
562 isochronous read requests.
566 isochronous read requests.
569 Counts number of full cache line writes to DRAM channel 0.
572 Counts number of full cache line writes to DRAM channel 1.
575 Counts number of full cache line writes to DRAM channel 2.
578 Counts number of full cache line writes to DRAM.
581 Counts number of partial cache line writes to DRAM channel 0.
584 Counts number of partial cache line writes to DRAM channel 1.
587 Counts number of partial cache line writes to DRAM channel 2.
590 Counts number of partial cache line writes to DRAM.
608 that has already been issued to the QMC.
609 In this instance, the QHL will send a priority update to QMC to expedite the request.
615 already been issued to the QMC.
616 In this instance, the QHL will send a priority update to QMC to expedite the request.
622 already been issued to the QMC.
623 In this instance, the QHL will send a priority update to QMC to expedite the request.
629 already been issued to the QMC.
630 In this instance, the QHL will send a priority update to QMC to expedite the request.
634 Home Logic to the local home.
638 due to lack of a VNA and VN0 credit.
644 due to lack of a VNA and VN0 credit.
649 Counts cycles the Quickpath outbound link 0 non-data response virtual
650 channel is stalled due to lack of a VNA and VN0 credit.
656 due to lack of a VNA and VN0 credit.
662 due to lack of a VNA and VN0 credit.
667 Counts cycles the Quickpath outbound link 1 non-data response virtual
668 channel is stalled due to lack of a VNA and VN0 credit.
686 stalled due to lack of VNA and VN0 credits.
691 Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual
692 channel is stalled due to lack of VNA and VN0 credits.
697 Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual
698 channel is stalled due to lack of VNA and VN0 credits.
704 stalled due to lack of VNA and VN0 credits.
709 Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual
710 channel is stalled due to lack of VNA and VN0 credits.
715 Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual
716 channel is stalled due to lack of VNA and VN0 credits.
741 Number of cycles that snoop packets incoming to the Quickpath Interface link
742 0 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT)
746 Number of cycles that snoop packets incoming to the Quickpath Interface link
747 1 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT)
751 Counts number of DRAM Channel 0 open commands issued either for read or write.
752 To read or write data, the referenced DRAM page must first be opened.
755 Counts number of DRAM Channel 1 open commands issued either for read or write.
756 To read or write data, the referenced DRAM page must first be opened.
759 Counts number of DRAM Channel 2 open commands issued either for read or write.
760 To read or write data, the referenced DRAM page must first be opened.
763 DRAM channel 0 command issued to CLOSE a page due to page idle timer
768 DRAM channel 1 command issued to CLOSE a page due to page idle timer
773 DRAM channel 2 command issued to CLOSE a page due to page idle timer
778 Counts the number of precharges (PRE) that were issued to DRAM channel 0
780 A page miss refers to a situation in which a page is currently open and
781 another page from the same bank needs to be opened.
786 Counts the number of precharges (PRE) that were issued to DRAM channel 1
788 A page miss refers to a situation in which a page is currently open and
789 another page from the same bank needs to be opened.
794 Counts the number of precharges (PRE) that were issued to DRAM channel 2
796 A page miss refers to a situation in which a page is currently open and
797 another page from the same bank needs to be opened.
802 Counts the number of times a read CAS command was issued on DRAM channel 0.
805 Counts the number of times a read CAS command was issued on DRAM channel 0
806 where the command issued used the auto-precharge (auto page close) mode.
809 Counts the number of times a read CAS command was issued on DRAM channel 1.
812 Counts the number of times a read CAS command was issued on DRAM channel 1
813 where the command issued used the auto-precharge (auto page close) mode.
816 Counts the number of times a read CAS command was issued on DRAM channel 2.
819 Counts the number of times a read CAS command was issued on DRAM channel 2
820 where the command issued used the auto-precharge (auto page close) mode.
827 where the command issued used the auto-precharge (auto page close) mode.
834 where the command issued used the auto-precharge (auto page close) mode.
841 where the command issued used the auto-precharge (auto page close) mode.
846 In order to keep correct data content, the data values have to be
852 In order to keep correct data content, the data values have to be
858 In order to keep correct data content, the data values have to be
862 Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close
864 PREALL is issued when the DRAM needs to be refreshed or needs to go
868 Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close
870 PREALL is issued when the DRAM needs to be refreshed or needs to go
874 Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close
876 PREALL is issued when the DRAM needs to be refreshed or needs to go