Lines Matching full:number
52 The number of PMCs available in each class and their widths need to be
60 .%N "Order Number: 253669-033US"
92 Counts the number of demand and DCU prefetch data reads of full
97 Counts the number of demand and DCU prefetch reads for ownership
101 Counts the number of demand and DCU prefetch instruction cacheline
104 WB Counts the number of writeback (modified to exclusive) transactions.
106 Counts the number of data cacheline reads generated by L2 prefetchers.
108 Counts the number of RFO requests generated by L2 prefetchers.
110 Counts the number of code reads generated by L2 prefetchers.
140 Configure the PMC to increment only if the number of configured
144 Configure the PMC to count the number of de-asserted to asserted
147 condition becomes true, irrespective of the number of clocks during
152 qualifier is present, making the counter increment when the number of
174 Counts the number of store buffer drains.
177 Counts number of loads delayed with at-Retirement block code.
193 Counts number of completed page walks due to load miss in the STLB.
196 Number of cache load STLB hits
199 Number of DTLB cache load misses where the low part of the linear to
203 Counts number of completed large page walks due to load miss in the STLB.
206 Counts the number of instructions with an architecturally-visible store
211 Counts the number of instructions with an architecturally-visible store
216 Counts the number of instructions exceeding the latency specified with
221 The event counts the number of retired stores that missed the DTLB.
227 Counts the number of Uops issued by the Register Allocation Table to the
232 Counts the number of cycles no Uops issued by the Register Allocation Table
238 Counts the number of fused Uops that were issued from the Register
242 Counts number of memory load instructions retired where the memory reference
247 Counts number of memory load instructions retired where the memory reference
251 Counts number of memory load instructions retired where the memory reference
256 Counts number of memory load instructions retired where the memory reference
262 Counts number of memory load instructions retired where the memory reference
269 Counts number of memory load instructions retired where the memory reference
274 Counts the number of FP Computational Uops Executed.
275 The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer
280 Counts number of MMX Uops executed.
283 Counts number of SSE and SSE2 FP uops executed.
286 Counts number of SSE2 integer uops executed.
289 Counts number of SSE FP packed uops executed.
292 Counts number of SSE FP scalar uops executed.
295 Counts number of SSE* FP single precision uops executed.
298 Counts number of SSE* FP double precision uops executed.
301 Counts number of 128 bit SIMD integer multiply operations.
304 Counts number of 128 bit SIMD integer shift operations.
307 Counts number of 128 bit SIMD integer pack operations.
310 Counts number of 128 bit SIMD integer unpack operations.
313 Counts number of 128 bit SIMD integer logical operations.
316 Counts number of 128 bit SIMD integer arithmetic operations.
319 Counts number of 128 bit SIMD integer shuffle and move operations.
322 Counts number of loads dispatched from the Reservation Station that bypass
326 Counts the number of delayed RS dispatches at the stage latch.
331 Counts the number of loads dispatched from the Reservation Station to the
338 Counts the number of cycles the divider is busy executing divide or square
342 Set 'edge =1, invert=1, cmask=1' to count the number of divides.
346 Counts the number of multiply operations executed.
351 Counts the number of instructions written into the instruction queue every
355 Counts number of instructions that require decoder 0 to be decoded.
362 This event counts the number of cycles during which instructions are written
364 Dividing this counter by the number of instructions written to the
365 instruction queue (INST_QUEUE_WRITES) yields the average number of
367 If this number is less than four and the pipe stalls, this indicates that the decoder is failing to
374 Counts number of loops that cant stream from the instruction queue.
377 Counts number of loads that hit the L2 cache.
383 Counts the number of loads that miss the L2 cache.
391 Counts the number of store RFO requests that hit the L2 cache.
397 Counts the number of store RFO requests that miss the L2 cache.
405 Counts number of instruction fetches that hit the L2 cache.
410 Counts number of instruction fetches that miss the L2 cache.
434 Counts number of L2 data demand loads where the cache line to be loaded is
439 Counts number of L2 data demand loads where the cache line to be loaded is
444 Counts number of L2 data demand loads where the cache line to be loaded is
449 Counts number of L2 data demand loads where the cache line to be loaded is
458 Counts number of L2 prefetch data loads where the cache line to be loaded is
462 Counts number of L2 prefetch data loads where the cache line to be loaded is
468 Counts number of L2 prefetch data loads where the cache line to be loaded is
472 Counts number of L2 prefetch data loads where the cache line to be loaded is
482 Counts number of L2 demand store RFO requests where the cache line to be
488 Counts number of L2 store RFO requests where the cache line to be loaded is
494 Counts number of L2 store RFO requests where the cache line to be loaded is
500 Counts number of L2 store RFO requests where the cache line to be loaded is
511 Counts number of L2 demand lock RFO requests where the cache line to be
515 Counts number of L2 lock RFO requests where the cache line to be loaded is
519 Counts number of L2 demand lock RFO requests where the cache line to be
523 Counts number of L2 demand lock RFO requests where the cache line to be
527 Counts number of L2 demand lock RFO requests where the cache line to be
534 Counts number of L1 writebacks to the L2 where the cache line to be written
538 Counts number of L1 writebacks to the L2 where the cache line to be written
542 Counts number of L1 writebacks to the L2 where the cache line to be written
546 Counts number of L1 writebacks to the L2 where the cache line to be written
571 Counts the number of thread cycles while the thread is not in a halt state.
656 Counts the number of misses in the STLB which causes a page walk.
659 Counts number of misses in the STLB which resulted in a completed page walk.
662 Counts the number of DTLB first level misses that hit in the second level TLB.
666 Number of DTLB misses caused by low part of address, includes references to 2M pages because 2M pag…
669 Counts number of misses in the STLB which resulted in a completed page walk for large pages.
677 Counts number of hardware prefetch requests dispatched out of the prefetch
681 Counts number of hardware prefetch requests that miss the L1D.
688 Counts number of prefetch requests triggered by the Finite State Machine and
695 Counts the number of lines brought into the L1 data cache.
699 Counts the number of modified lines brought into the L1 data cache.
703 Counts the number of modified lines evicted from the L1 data cache due to
708 Counts the number of modified lines evicted from the L1 data cache due to
713 Counts the number of cacheable load lock speculated instructions accepted
717 Counts the number of cacheable load lock speculated or retired instructions
730 Counts the number of cycles that cacheline in the L1 data cache unit is
735 Counts the number of completed I/O transactions.
756 Counts number of large ITLB hits.
759 Counts the number of misses in all levels of the ITLB which causes a page
763 Counts number of misses in all levels of the ITLB which resulted in a
779 Counts the number of regen stalls.
785 Counts the number of conditional near branch instructions executed, but not
793 Counts the number of executed indirect near branch instructions that are not
824 Counts the number of mispredicted conditional near branch instructions
832 Counts the number of executed mispredicted indirect near branch instructions
858 Counts the number of mispredicted near branch instructions that were
862 Counts the number of Allocator resource related stalls.
875 This event counts the number of cycles when the number of instructions in
885 This event counts the number of cycles that a resource related stall will
886 occur due to the number of store instructions reaching the limit of the
894 Counts the number of cycles while execution was stalled due to writing the
903 Counts the number of cycles while execution was stalled due to other
907 Counts the number of instructions decoded that are macro-fused but not
911 Counts number of times a BACLEAR was forced by the Instruction Queue.
922 Counts the number of micro-ops delivered by loop stream detector
926 Counts the number of ITLB flushes
929 Counts number of L1D writebacks to the uncore.
932 Counts number of Uops executed that were issued on port 0.
936 Counts number of Uops executed that were issued on port 1.
940 Counts number of Uops executed that were issued on port 2.
945 Counts number of Uops executed that were issued on port 3.
950 Counts number of Uops executed that where issued on port 4.
962 Counts number of Uops executed that where issued on port 5.
970 Counts number of Uops executed that where issued on port 0, 1, or 5.
974 Counts number of Uops executed that where issued on port 2, 3, or 4.
977 Counts number of cycles the SQ is full to handle off-core requests.
1011 Counts the number of MMX instructions retired.
1014 Counts the number of floating point computational operations retired:
1020 Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
1028 Counts the number of retirement slots used each cycle
1031 Counts number of macro-fused uops retired.
1037 Counts the number of machine clears due to memory order conflicts.
1040 Counts the number of times that a program writes to a code section.
1049 Counts the number of conditional branch instructions retired.
1052 Counts the number of direct & indirect near unconditional calls retired
1055 Counts the number of branch instructions retired
1079 Counts the number of retired instructions that missed the ITLB when the
1083 Counts number of retired loads that hit the L1 data cache.
1086 Counts number of retired loads that hit the L2 data cache.
1089 Counts number of retired loads that hit their own, unshared lines in the L3
1093 Counts number of retired loads that hit in a sibling core's L2 (on die core).
1098 Counts number of retired loads that miss the L3 cache.
1102 Counts number of retired loads that miss the L1D and the address is located
1107 Counts the number of retired loads that missed the DTLB.
1130 Counts the number of instructions decoded, (but not necessarily executed or
1134 Counts the number of Uops decoded by the Microcode Sequencer, MS.
1139 Counts number of stack pointer (ESP) instructions decoded: push , pop , call
1146 Counts number of stack pointer (ESP) sync operations where an ESP
1151 Counts the number of cycles during which execution stalled due to several
1159 This event counts the number of cycles instruction execution latency became
1164 Counts the number of cycles when ROB read port stalls occurred, which did
1187 Counts the number of stall cycles due to the lack of renaming resources for
1194 Counts the number of times the ES segment register is renamed.
1200 Counts the number of branch instructions decoded.
1203 Counts number of times the Branch Prediction Unit missed predicting a call
1207 Counts the number of times the front end is resteered, mainly when the
1217 Counts number of Branch Address Calculator clears (BACLEAR) asserted due to
1258 Counts the number of cache lines allocated in the L2 cache in the S (shared)
1262 Counts the number of cache lines allocated in the L2 cache in the E
1266 Counts the number of cache lines allocated in the L2 cache.
1284 Counts the number of SQ lock splits across a cache line.
1291 Counts the number of floating point operations executed that required
1300 Counts number of floating point micro-code assist when the output value
1304 Counts number of floating point micro-code assist when the input value (one
1308 Counts number of SID integer 64 bit packed multiply operations.
1311 Counts number of SID integer 64 bit packed shift operations.
1314 Counts number of SID integer 64 bit pack operations.
1317 Counts number of SID integer 64 bit unpack operations.
1320 Counts number of SID integer 64 bit logical operations.
1323 Counts number of SID integer 64 bit arithmetic operations.
1326 Counts number of SID integer 64 bit shift or move operations.
1334 Counts the number of store forwards.
1337 Counts the number of loads blocked by a preceding store with unknown data.
1340 Counts the number of loads blocked by a preceding store address.
1346 Counts the number of misaligned load references
1349 Counts the number of misaligned store references
1352 Counts the number of misaligned memory references
1355 This event counts the number of load operations delayed caused by preceding
1370 Counts the number of loads that memory disambiguration succeeded
1373 Counts the number of times the memory disambiguration watchdog kicked in.
1380 Number of interrupt received
1383 Number of cycles interrupt are masked
1386 Number of cycles interrupts are pending and masked
1389 Counts number of L2 store RFO requests where the cache line to be loaded is
1411 Number of DTLB cache misses where the low part of the linear to physical
1415 Number of DTLB misses where the high part of the linear to physical address
1419 Counts number of completed large page walks due to misses in the STLB.
1422 Counts number of SSE NTA prefetch/weakly-ordered instructions which missed
1426 Counts number of SSE non temporal stores
1478 Counts the number of ITLB misses that hit in the second level TLB.
1481 Number of ITLB misses where the low part of the linear to physical address
1485 Number of ITLB misses where the high part of the linear to physical address
1489 Counts number of completed large page walks due to misses in the STLB.
1492 Counts number of offcore demand data read requests.
1496 Counts number of offcore demand code read requests.
1500 Counts number of offcore demand RFO requests.
1504 Counts number of offcore read requests.
1508 Counts number of offcore RFO requests.
1512 Counts number of offcore uncached memory requests.
1530 Counts number of TPR reads
1533 Counts number of TPR writes one or two micro-ops.
1537 Counts the number of macro-fusion assists
1541 Counts the number of bogus branches.
1562 Counts the number of L2 secondary misses that hit the Super Queue.
1565 Counts the number of L2 secondary misses during the Super Queue filling L2.
1568 Counts number of Super Queue LRU hints sent to L3.
1571 Counts the number of SQ L2 fills dropped due to L2 busy.
1574 Counts number of segment register loads.