Lines Matching full:loads

177 Counts number of loads delayed with at-Retirement block code.
178 The following loads need to be executed at retirement and wait for all
184 Cacheable loads delayed with L1D block code
204 .It Li MEM_INST_RETIRED.LOADS
322 Counts number of loads dispatched from the Reservation Station that bypass
331 Counts the number of loads dispatched from the Reservation Station to the
335 Counts all loads dispatched from the Reservation Station.
377 Counts number of loads that hit the L2 cache.
378 L2 loads include both L1D demand misses as well as L1D prefetches.
379 L2 loads can be rejected for various reasons.
380 Only non rejected loads are counted.
383 Counts the number of loads that miss the L2 cache.
384 L2 loads include both L1D demand misses as well as L1D prefetches.
385 .It Li L2_RQSTS.LOADS
388 L2 loads include both L1D demand misses as well as L1D prefetches.
434 Counts number of L2 data demand loads where the cache line to be loaded is
436 L2 demand loads are both L1D demand misses and L1D prefetches.
439 Counts number of L2 data demand loads where the cache line to be loaded is
441 L2 demand loads are both L1D demand misses and L1D prefetches.
444 Counts number of L2 data demand loads where the cache line to be loaded is
446 L2 demand loads are both L1D demand misses and L1D prefetches.
449 Counts number of L2 data demand loads where the cache line to be loaded is
451 L2 demand loads are both L1D demand misses and L1D prefetches.
455 L2 demand loads are both L1D demand misses and L1D prefetches.
458 Counts number of L2 prefetch data loads where the cache line to be loaded is
462 Counts number of L2 prefetch data loads where the cache line to be loaded is
468 Counts number of L2 prefetch data loads where the cache line to be loaded is
472 Counts number of L2 prefetch data loads where the cache line to be loaded is
643 cache, including all loads and stores with any memory types.
1083 Counts number of retired loads that hit the L1 data cache.
1086 Counts number of retired loads that hit the L2 data cache.
1089 Counts number of retired loads that hit their own, unshared lines in the L3
1093 Counts number of retired loads that hit in a sibling core's L2 (on die core).
1098 Counts number of retired loads that miss the L3 cache.
1102 Counts number of retired loads that miss the L1D and the address is located
1107 Counts the number of retired loads that missed the DTLB.
1109 This event counts loads from cacheable memory only.
1110 The event does not count loads by software prefetches.
1233 Counts L2 load operations due to HW prefetch or demand loads.
1337 Counts the number of loads blocked by a preceding store with unknown data.
1340 Counts the number of loads blocked by a preceding store address.
1364 All loads delayed due to store blocks
1370 Counts the number of loads that memory disambiguration succeeded
1574 Counts number of segment register loads.