Lines Matching +full:data +full:- +full:only

18 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
92 Counts the number of demand and DCU prefetch data reads of full
93 and partial cachelines as well as demand data page table entry
95 Does not count L2 data read prefetches or instruction fetches.
98 (RFO) requests generated by a write to data cacheline.
106 Counts the number of data cacheline reads generated by L2 prefetchers.
113 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
128 by forwarded data following a cross package snoop where no modified
137 Non-DRAM requests that were serviced by IOH.
140 Configure the PMC to increment only if the number of configured
144 Configure the PMC to count the number of de-asserted to asserted
146 If specified, the counter will increment only once whenever a
171 .Bl -tag -width indent
177 Counts number of loads delayed with at-Retirement block code.
206 Counts the number of instructions with an architecturally-visible store
211 Counts the number of instructions with an architecturally-visible store
243 missed L3 and data source is unknown.
244 Available only for CPUID signature 06_2EH
248 hit modified data in a sibling core residing on the same socket.
253 Only counts locally homed lines.
271 Available only for CPUID signature 06_2EH
328 one-cycle delayed staging latch before it is written into the LB.
368 decode enough instructions per cycle to sustain the 4-wide pipeline.
380 Only non rejected loads are counted.
393 Count includes WC memory requests, where the data is not fetched but the
419 Counts L2 prefetch hits for both code and data.
422 Counts L2 prefetch misses for both code and data.
425 Counts all L2 prefetches for both code and data.
428 Counts all L2 misses for both code and data.
431 Counts all L2 requests for both code and data.
434 Counts number of L2 data demand loads where the cache line to be loaded is
439 Counts number of L2 data demand loads where the cache line to be loaded is
444 Counts number of L2 data demand loads where the cache line to be loaded is
449 Counts number of L2 data demand loads where the cache line to be loaded is
454 Counts all L2 data demand requests.
458 Counts number of L2 prefetch data loads where the cache line to be loaded is
462 Counts number of L2 prefetch data loads where the cache line to be loaded is
468 Counts number of L2 prefetch data loads where the cache line to be loaded is
472 Counts number of L2 prefetch data loads where the cache line to be loaded is
479 Counts all L2 data requests.
556 due to a L2 hardware-prefetch.
557 Because cache hierarchy, cache sizes and other implementation-specific
559 see Table A-1
565 line fills due to L2 hardware-prefetches.
566 Because cache hierarchy, cache sizes and other implementation-specific
568 see Table A-1
574 see Table A-1
578 see Table A-1
581 Counts L1 data cache read requests where the cache line to be loaded is in
583 Counter 0, 1 only
586 Counts L1 data cache read requests where the cache line to be loaded is in
588 Counter 0, 1 only
591 Counts L1 data cache read requests where the cache line to be loaded is in
593 Counter 0, 1 only
596 Counts L1 data cache read requests where the cache line to be loaded is in
598 Counter 0, 1 only
601 Counts L1 data cache read requests.
602 Counter 0, 1 only
605 Counts L1 data cache store RFO requests where the cache line to be loaded is
607 Counter 0, 1 only
610 Counts L1 data cache store RFO requests where the cache line to be loaded is
612 Counter 0, 1 only
615 Counts L1 data cache store RFO requests where cache line to be loaded is in
617 Counter 0, 1 only
620 Counts retired load locks that hit in the L1 data cache or hit in an already
623 The initial load will pull the lock into the L1 data cache.
624 Counter 0, 1 only
627 Counts L1 data cache retired load locks that hit the target cache line in
629 Counter 0, 1 only
632 Counts L1 data cache retired load locks that hit the target cache line in
634 Counter 0, 1 only
637 Counts L1 data cache retired load locks that hit the target cache line in
639 Counter 0, 1 only
642 Counts all references (uncached, speculated and retired) to the L1 data
644 The event counts memory accesses only when they are actually performed.
646 is only counted once.
647 The event does not include non- memory accesses, such as I/O accesses.
648 Counter 0, 1 only
651 Counts all data reads and writes (speculated and retired) from cacheable
653 Counter 0, 1 only
663 This event is only relevant if the core contains multiple DTLB levels.
672 Counts load operations sent to the L1 data cache while a previous SSE
695 Counts the number of lines brought into the L1 data cache.
696 Counter 0, 1 only
699 Counts the number of modified lines brought into the L1 data cache.
700 Counter 0, 1 only
703 Counts the number of modified lines evicted from the L1 data cache due to
705 Counter 0, 1 only
708 Counts the number of modified lines evicted from the L1 data cache due to
710 Counter 0, 1 only
725 Counter 0, 1 only.
730 Counts the number of cycles that cacheline in the L1 data cache unit is
732 Counter 0, 1 only.
744 An instruction fetch miss is counted only once and not once for every cycle
819 This includes only instructions and not micro-op branches.
843 Counts mispredicted non-indirect near calls executed, (should always be 0).
888 The stall ends when a store instruction commits its data to the cache or memory.
891 Counts the cycles of stall due to re- order buffer full.
895 floating-point unit (FPU) control word.
907 Counts the number of instructions decoded that are macro-fused but not
913 based on a static scheme and dynamic data provided by the L2 Branch
922 Counts the number of micro-ops delivered by loop stream detector
942 This is a core count only and can not be collected per thread.
947 This is a core count only and can not be collected per thread.
952 This is a core count only and can not be collected per thread.
958 Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count
959 P0-4 stalls.
966 Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 sta…
967 cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls.
977 Counts number of cycles the SQ is full to handle off-core requests.
980 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
997 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
1002 See Table A-1
1016 sub-operations of complex floating point instructions like transcendental
1020 Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
1022 Most instructions are composed of one or two micro-ops.
1031 Counts number of macro-fused uops retired.
1041 Self-modifying code causes a sever penalty in all Intel 64 and IA-32
1046 See Table A-1
1058 See Table A-1
1064 Counts SIMD packed single-precision floating point Uops retired.
1067 Counts SIMD calar single-precision floating point Uops retired.
1070 Counts SIMD packed double- precision floating point Uops retired.
1073 Counts SIMD scalar double-precision floating point Uops retired.
1076 Counts 128-bit SIMD vector integer Uops retired.
1083 Counts number of retired loads that hit the L1 data cache.
1086 Counts number of retired loads that hit the L2 data cache.
1109 This event counts loads from cacheable memory only.
1114 Counts the first floating-point instruction following any MMX instruction.
1116 floating-point and MMX technology states.
1119 Counts the first MMX instruction following a floating-point instruction.
1121 floating-point and MMX technology states.
1127 floating-point and MMX technology states.
1165 not allow new micro-ops to enter the out-of-order pipeline.
1167 the same cycle and prevent the stalled micro-ops from entering the pipe.
1168 In such a case, micro-ops retry entering the execution pipe in the next
1169 cycle and the ROB-read port stall is counted again.
1178 read port stalls occurred, which did not allow new micro-ops to enter the
1181 Cycles floating-point unit (FPU) status word stalls occurred.
1190 segment occurs, a stall occurs in the front-end of the pipeline until the
1292 micro-code assist intervention.
1300 Counts number of floating point micro-code assist when the output value
1304 Counts number of floating point micro-code assist when the input value (one
1331 .Bl -tag -width indent
1337 Counts the number of loads blocked by a preceding store with unknown data.
1356 stores whose addresses are known but whose data is unknown, and preceding
1398 Counts micro-ops decoded by decoder 0.
1401 Counts L1 data cache store RFO requests where the cache line to be loaded is
1403 Counter 0, 1 only
1407 Counts L1 data cache store RFO requests.
1408 Counter 0, 1 only
1422 Counts number of SSE NTA prefetch/weakly-ordered instructions which missed
1423 the L1 data cache.
1443 Counts weighted cycles of offcore demand data read requests.
1492 Counts number of offcore demand data read requests.
1516 .It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA
1518 Counts weighted cycles of snoopq requests for data.
1519 Counter 0 only Use cmask=1 to count cycles not empty.
1523 Counter 0 only Use cmask=1 to count cycles not empty.
1527 Counter 0 only Use cmask=1 to count cycles not empty.
1533 Counts number of TPR writes one or two micro-ops.
1537 Counts the number of macro-fusion assists
1538 Counts SIMD packed single- precision floating point Uops retired.
1550 Count L2 HW data prefetcher triggered