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40 CPUs contain PMCs conforming to version 2 of the
43 These CPUs may contain up to two classes of PMCs:
48 Programmable counters that may be configured to count one of a defined
49 set of hardware events.
52 The number of PMCs available in each class and their widths need to be
89 Configure the PMC to increment only if the number of configured
93 Configure the PMC to count the number of de-asserted to asserted
94 transitions of the conditions expressed by the other qualifiers.
96 condition becomes true, irrespective of the number of clocks during
99 Invert the sense of comparison when the
101 qualifier is present, making the counter increment when the number of
113 If neither of the
124 is one of:
140 is one of:
156 is one of:
174 contains one or more of the following letters:
194 comprises of the following keywords separated by
212 comprises the one of the following keywords:
226 The number of times the front end is resteered.
229 The number of byte sequences mistakenly detected as taken branch
233 The number of branch instructions that were mispredicted when
237 The number of mispredicted
242 The number of
247 The number of conditional branches executed, but not necessarily retired.
250 The number of mispredicted conditional branches executed.
253 The number of indirect
258 The number of indirect branch instructions executed.
261 The number of mispredicted indirect branch instructions executed.
264 The number of branch instructions decoded.
267 The number of branches executed, but not necessarily retired.
271 The number of branch instructions retired.
276 The number of mispredicted branch instructions retired.
280 The number of not taken branch instructions retired that were
287 The number of not taken branch instructions retired that were
291 The number of taken branch instructions retired that were correctly
295 The number of taken branch instructions retired.
298 The number of mispredicted branch instructions that were executed.
301 The number of mispredicted
306 The number of
311 The number of
316 The number of branch predicted taken with bubble 1.
319 The number of branch predicted taken with bubble 2.
322 The number of cycles during which the core did not have any pending
326 The number of Bus Not Ready signals asserted on the bus.
329 The number of bus cycles during which the processor is receiving data.
332 The number of bus cycles during which the Data Ready signal is asserted
336 The number of bus cycles during which the processor drives the
341 The number of bus cycles during which the processor drives the
346 The number of core cycles during which I/O requests wait in the bus
353 The number of bus cycles during which the
361 The number of pending full cache line read transactions on the bus
368 The number of partial bus transactions.
374 The number of instruction fetch full cache line bus transactions.
380 The number of invalidate bus transactions.
386 The number of partial write bus transactions.
392 The number of deferred bus transactions.
398 The number of burst transactions.
404 The number of memory bus transactions.
410 The number of bus transactions of any kind.
416 The number of burst read transactions.
422 The number of completed I/O bus transactions due to
432 The number of Read For Ownership bus transactions.
445 The number of times the L1 data cache is snooped by the other core in
450 The number of bus cycles when the core is not in the halt state.
455 The number of core cycles while the core is not in a halt state.
459 The number of bus cycles during which the core remains unhalted and
463 The number of cycles the divider is busy.
467 The number of cycles during which interrupts are disabled.
470 The number of cycles during which there were pending interrupts while
474 The number of cycles for which an instruction fetch stalls.
477 The number of floating point operations that used data immediately
481 The number of delayed bypass penalty cycles that a load operation incurred.
484 The number of times SIMD operations use data immediately after data,
488 The number of divide operations executed.
492 The number of Data TLB misses, including misses that result from
496 The number of level 0 DTLB misses due to load operations.
499 The number of Data TLB misses due to load operations.
502 The number of Data TLB misses due to store operations.
505 The number of Enhanced Intel SpeedStep Technology transitions.
508 The number of automatic additions to the
513 The number of times the
526 The number of snoop responses to bus transactions.
529 The number of floating point operations executed that needed
533 The number of floating point computational micro-ops executed.
537 The number of transitions from MMX instructions to floating point
541 The number of transitions from floating point instructions to MMX
545 The number of hardware interrupts received.
548 The number of cycles the divider is busy and no other execution unit
553 The number of cycles the instruction length decoder stalled due to a
557 The number of cycles during which the instruction queue is full.
561 The number of instructions retired.
565 The number of instructions retired that contained a load operation.
568 The number of instructions retired that did not contain a load or a
572 The number of instructions retired that contained a store operation.
576 The number of instructions retired while in VMX root operation.
579 The number of ITLB flushes.
582 The number of instruction fetches from large pages that miss the
586 The number of instruction fetches from both large and small pages that
590 The number of instruction fetches from small pages that miss the ITLB.
593 The number of retired instructions that missed the ITLB when they were
597 The number of references to L1 data cache counting loads and stores of
601 The number of data reads and writes to cacheable memory.
604 The number of locked reads from cacheable memory.
607 The number of cycles during which any cache line is locked by any
611 The number of data reads from cacheable memory excluding locked
615 The number of data writes to cacheable memory excluding locked
619 The number of modified cache lines evicted from L1 data cache.
622 The number of modified lines allocated in L1 data cache.
625 The total number of outstanding L1 data cache misses at any clock.
628 The number of times L1 data cache requested to prefetch a data cache
632 The number of lines brought into L1 data cache.
635 The number of load operations that span two cache lines.
638 The number of store operations that span two cache lines.
641 The number of instruction fetch unit misses.
644 The number of instruction fetches.
647 The number of cycles that the L2 address bus is in use.
650 The number of cycles during which the L2 data bus is busy transferring
657 The number of instruction cache line requests from the instruction
665 The number of L2 cache read requests from L1 cache and L2
672 The number of cache lines allocated in L2 cache.
678 The number of L2 cache lines evicted.
684 The number of locked accesses to cache lines that miss L1 data
688 The number of L2 cache line modifications.
694 The number of modified lines evicted from L2 cache.
697 The number of cycles during which no L2 cache requests were pending
705 The number of L2 cache requests that were rejected.
712 The number of completed L2 cache requests.
716 The number of completed L2 cache demand requests from this core that
722 The number of completed L2 cache demand requests from this core.
729 The number of store operations that miss the L1 cache and request data
733 The number of loads blocked by the L1 data cache.
736 The number of loads that partially overlap an earlier store or are
740 The number of loads blocked by preceding stores whose address is yet
744 The number of loads blocked by preceding stores to the same address
748 The number of load operations that were blocked until retirement.
751 The number of load operations that conflicted with an prefetch to the
755 The number of times a program writes to a code section.
758 The number of times the execution pipeline was restarted due to a
762 The number of complex instructions decoded.
765 The number of instructions decoded.
768 The number of cycles during which memory disambiguation misprediction
772 The number of load operations that were successfully disambiguated.
775 The number of retired loads that missed the DTLB.
778 The number of retired load operations that missed L1 data cache and
783 The number of retired load operations that missed L1 data cache.
787 The number of load operations that missed L2 cache and that caused a
791 The number of load operations that missed L2 cache.
794 The number of multiply operations executed.
798 The number of page walks executed due to an ITLB or DTLB miss.
801 The number of cycles spent in a page walk caused by an ITLB or DTLB
805 The number of downward prefetches issued from the Data Prefetch Logic
809 The number of upward prefetches issued from the Data Prefetch Logic
813 The number of stall cycles due to any of
821 The number of cycles execution stalled due to a flag register induced
825 The number of times the floating point status word was written.
828 The number of stalls due to other RAT resource serialization not
832 The number of cycles of added instruction execution latency due to the
833 use of a register that was partially written by previous instructions.
836 The number of cycles when ROB read port stalls occurred.
839 The number of cycles during which any resource related stall
843 The number of cycles stalled due to branch misprediction.
846 The number of cycles stalled due to writing the floating point control
850 The number of cycles during which the number of loads and stores in
854 The number of cycles when the reorder buffer was full.
857 The number of cycles during which the RS was full.
860 The number of micro-ops dispatched for execution.
863 The number of cycles micro-ops were dispatched for execution on port
867 The number of cycles micro-ops were dispatched for execution on port
871 The number of cycles micro-ops were dispatched for execution on port
875 The number of cycles micro-ops were dispatched for execution on port
879 The number of cycles micro-ops were dispatched for execution on port
883 The number of cycles micro-ops were dispatched for execution on port
887 The number of cycles while the store buffer is draining.
890 The number of segment register loads.
893 The number of times the any segment register was renamed.
896 The number of times the
901 The number of times the
906 The number of times the
911 The number of times the
916 The number of stalls due to lack of resource to rename any segment
920 The number of stalls due to lack of renaming resources for the
925 The number of stalls due to lack of renaming resources for the
930 The number of stalls due to lack of renaming resources for the
935 The number of stalls due to lack of renaming resources for the
943 Then number of computational SSE2 packed double precision instructions
947 Then number of computational SSE2 packed single precision instructions
951 Then number of computational SSE2 scalar double precision instructions
955 Then number of computational SSE2 scalar single precision instructions
959 The number of retired SIMD instructions that use MMX registers.
962 The number of streaming SIMD instructions retired.
965 The number of SSE2 packed double precision instructions retired.
968 The number of SSE packed single precision instructions retired.
971 The number of SSE2 scalar double precision instructions retired.
974 The number of SSE scalar single precision instructions retired.
977 The number of SSE2 vector instructions retired.
980 The number of saturated arithmetic SIMD instructions retired.
983 The number of SIMD saturated arithmetic micro-ops executed.
986 The number of SIMD micro-ops executed.
989 The number of SIMD packed arithmetic micro-ops executed.
992 The number of SIMD packed logical micro-ops executed.
995 The number of SIMD packed multiply micro-ops executed.
998 The number of SIMD pack micro-ops executed.
1001 The number of SIMD packed shift micro-ops executed.
1004 The number of SIMD unpack micro-ops executed.
1010 The number of times the bus stalled for snoops.
1013 The number of
1018 The number of
1023 The number of
1028 The number of times SSE non-temporal store instructions were executed.
1031 The number of times the
1036 The number of times the
1041 The number of times the
1046 The number of cycles while a store was waiting for another store to be
1050 The number of cycles while a store was blocked due to a conflict with
1054 The number of thermal trips.
1057 The number of micro-ops retired that fused a load with another
1061 The number of store address calculations that fused into one micro-op.
1064 The number of times retired instruction pairs were fused into one
1068 The number of fused micro-ops retired.
1071 The number of non-fused micro-ops retired.
1074 The number of micro-ops retired.
1077 The number of floating point computational instructions retired.
1080 The number of