Lines Matching full:during
96 condition becomes true, irrespective of the number of clocks during
322 The number of cycles during which the core did not have any pending
329 The number of bus cycles during which the processor is receiving data.
332 The number of bus cycles during which the Data Ready signal is asserted
336 The number of bus cycles during which the processor drives the
341 The number of bus cycles during which the processor drives the
346 The number of core cycles during which I/O requests wait in the bus
353 The number of bus cycles during which the
459 The number of bus cycles during which the core remains unhalted and
467 The number of cycles during which interrupts are disabled.
470 The number of cycles during which there were pending interrupts while
557 The number of cycles during which the instruction queue is full.
607 The number of cycles during which any cache line is locked by any
650 The number of cycles during which the L2 data bus is busy transferring
697 The number of cycles during which no L2 cache requests were pending
768 The number of cycles during which memory disambiguation misprediction
839 The number of cycles during which any resource related stall
850 The number of cycles during which the number of loads and stores in
857 The number of cycles during which the RS was full.