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44 CPUs contain PMCs conforming to version 1 of the
57 CPUs conforming to version 1 of the
59 performance measurement architecture contain two programmable PMCs of
82 Configure the PMC to increment only if the number of configured
86 Configure the PMC to count the number of de-asserted to asserted
87 transitions of the conditions expressed by the other qualifiers.
89 condition becomes true, irrespective of the number of clocks during
92 Invert the sense of comparison when the
94 qualifier is present, making the counter increment when the number of
106 If neither of the
117 is one of:
132 is one of:
147 is one of:
164 contains one or more of the following letters:
186 The number of BAClear conditions asserted.
189 The number of branches for which the branch table buffer did not
193 The number of branch instructions executed that were mispredicted at
197 The number of bogus branches.
200 The number of
205 The number of
210 The number of conditional branch instructions executed.
213 The number of conditional branch instructions executed that were mispredicted.
216 The number of indirect
221 The number of indirect branches executed.
224 The number of indirect branch instructions executed that were mispredicted.
227 The number of branch instructions executed including speculative branches.
230 The number of branch instructions decoded.
234 The number of branch instructions retired.
239 The number of mispredicted branch instructions retired.
243 The number of taken and mispredicted branches retired.
246 The number of branch instructions executed and mispredicted at
250 The number of return branch instructions that were mispredicted at the
254 The number of return branch instructions executed.
257 The number of return branch instructions executed that were mispredicted.
260 The number of taken branches retired.
263 The number of external bus cycles while BNR (bus not ready) was asserted.
266 The number of external bus cycles while DRDY was asserted.
270 The number of cycles during which the processor is busy receiving data.
273 The number of external bus cycles while the bus lock signal was asserted.
276 The number of cycles when there is no transaction from the core.
282 The weighted cycles of cacheable bus data read requests
293 The number of snoop responses to bus transactions.
296 The number of completed bus transactions.
299 The number of read bus transactions.
302 The number of completed burst transactions.
306 The number of completed deferred transactions.
312 The number of completed I/O transactions counting both reads and
328 The number of completed memory transactions.
334 The number of completed partial transactions.
340 The number of completed partial write transactions.
346 The number of completed read-for-ownership transactions.
349 The number of completed write-back transactions from the data cache
353 The number of cycles the divider is busy.
357 The number of cycles while interrupts were disabled.
360 The number of cycles while interrupts were disabled and interrupts
364 The number of data cache unit snoops to L1 cache lines in the shared
369 The number of cacheable locked read operations to invalid state.
372 The number of cacheable L1 data read operations.
378 The number of M state data cache lines that were evicted.
381 The number of M state data cache lines that were allocated.
387 The number of data cache line replacements.
390 The number of cacheable read and write operations to L1 data cache.
393 The number of L1 data reads and writes, both cacheable and
397 The number of core cycles during which the data bus was busy.
400 The number of cycles during which the data bus was busy transferring
404 The number of divide operations including speculative operations for
409 The number of data references that missed the TLB.
412 The number of ESP folding instructions decoded.
415 Count the number of Intel Enhanced SpeedStep transitions.
418 can be one of the following values:
429 The number of floating point operations that required microcode
434 The number of X87 floating point compute instructions retired.
438 The number of floating point computational instructions executed.
441 The number of transitions from X87 to MMX.
444 The number of fused load uops retired.
447 The number of fused store uops retired.
450 The number of fused uops retired.
453 The number of hardware interrupts received.
456 The number of instruction fetch misses in the instruction cache and
460 The number of instruction fetches from the instruction cache and
464 The number of cycles the instruction fetch unit was stalled while
468 The number of instruction length decoder stalls.
471 The number of instruction TLB misses.
474 The number of instructions decoded.
478 The number of instructions retired.
482 The number of L1 prefetch request due to data cache misses.
485 The number of L2 address strobes.
491 The number of instruction fetches by the instruction fetch unit from
498 The number of L2 cache reads.
504 The number of L2 cache lines allocated.
510 The number of L2 cache lines evicted.
513 The number of L2 M state cache lines allocated.
519 The number of L2 M state cache lines evicted.
526 The number of cycles there was no request to access L2 cache.
533 The number of cycles the L2 cache was busy and rejecting new requests.
540 The number of L2 cache requests.
546 The number of L2 cache writes including speculative writes.
549 The number of load operations delayed due to store buffer blocks.
552 The number of cache misses for references to the last level cache,
556 The number of references to the last level cache,
563 The number of EMMX instructions executed.
566 The number of transitions from MMX to X87.
569 The number of MMX instructions executed excluding
576 The number of MMX instructions retired.
579 The number of misaligned data memory references, counting loads and
583 The number of multiply operations include speculative floating point
589 The number of non-halted bus cycles.
593 The number of hardware prefetch requests issued in backward streams.
596 The number of hardware prefetch requests issued in forward streams.
599 The number of cycles where there is a resource related stall.
602 The number of cycles while draining store buffers.
605 The number of SSE/SSE2 packed double precision instructions retired.
608 The number of SSE/SSE2 packed double precision compute instructions
612 The number of SSE/SSE2 scalar double precision instructions retired.
615 The number of SSE/SSE2 scalar double precision compute instructions
619 The number of SSE/SSE2 packed single precision compute instructions
623 The number of SSE/SSE2 scalar single precision instructions retired,
627 The number of SSE/SSE2 scalar single precision instructions retired.
630 The number of SSE/SSE2 single precision compute instructions retired.
633 The number of SSE2 128-bit integer instructions retired.
636 The number of SIMD integer packed arithmetic instructions executed.
639 The number of SIMD integer pack operations instructions executed.
642 The number of SIMD integer packed logical instructions executed.
645 The number of SIMD integer packed multiply instructions executed.
648 The number of SIMD integer packed shift instructions executed.
651 The number of SIMD integer saturating instructions executed.
654 The number of SIMD integer unpack instructions executed.
657 The number of times self-modifying code was detected.
660 The number of times an SSE streaming store instruction missed all caches.
663 The number of SSE streaming store instructions executed.
666 The number of times
671 The number of
676 The number of times
681 The number of
686 The number of times
691 The number of
696 The number of segment register loads.
699 The number of non-halted bus cycles of this code while the other core
706 The number of unfusion events.
709 The number of core clock cycles when the clock signal on a specific
714 The number of micro-ops retired.