Lines Matching full:number
53 The number of PMCs available in each class and their widths need to be
61 .%N "Order Number 325462-050US"
91 Configure the PMC to increment only if the number of configured
95 Configure the PMC to count the number of de-asserted to asserted
98 condition becomes true, irrespective of the number of clocks during
103 qualifier is present, making the counter increment when the number of
228 The number of retired loads that were
238 The number of retire stores that experienced.
242 The number of retire loads that experienced.
246 The number of retired memory operations with lock semantics.
252 The number of retired stores that are delayed
256 The number of load uops reissued from Rehabq.
259 The number of store uops reissued from Rehabq.
262 The number of load ops retired that miss in L1
267 The number of load micro-ops retired that hit L2.
270 The number of load micro-ops retired that missed L2.
273 The number of load ops retired that had DTLB miss.
276 The number of load ops retired that had UTLB miss.
279 The number of load ops retired that got data
283 The number of load ops retired.
286 The number of store ops retired.
290 Page walk duration divided by number of page walks is the average duration of
293 Set Edge to count the number of page walks.
298 Page walk duration divided by number of page walks is the average duration of
302 The number of times a data (D) page walk or an instruction (I) page walk is
304 Since a page walk implies a TLB miss, the number of TLB misses can be counted
305 by counting the number of pagewalks.
308 the total number of L2 cache references and the number of L2 cache misses
313 The number of requests originating from the core that
318 The number of demand and prefetch
325 The number of demand and L1 prefetcher
338 The number of core cycles while the core is not in a halt state.
344 The number of reference cycles that the core is not in a halt state.
351 The number of instruction fetches from the instruction cache.
354 The number of instruction fetches that miss the Instruction cache or produce
361 The number of instruction fetches, including uncacheable fetches.
364 The number of cycles the NIP stalls because of an icache miss.
375 The number of instructions that retire execution.
382 The number of micro-ops retired that were supplied from MSROM.
385 The number of micro-ops retired.
388 The number of times that a program writes to a code section.
393 The number of times that pipeline was cleared due to memory
397 The number of times that pipeline stalled due to FP operations
401 The number of times that pipeline stalled due to due to any causes
405 The number of branch instructions retired.
408 The number of branch instructions retired that were conditional
412 The number of far branch instructions retired.
415 The number of branch instructions retired that were near indirect
419 The number of near RET branch instructions retired.
422 The number of near CALL branch instructions retired.
425 The number of near indirect CALL branch instructions retired.
428 The number of near relative CALL branch instructions retired.
431 The number of branch instructions retired that were conditional
435 The number of mispredicted branch instructions retired.
438 The number of mispredicted branch instructions retired that were
442 The number of mispredicted far branch instructions retired.
445 The number of mispredicted branch instructions retired that were
449 The number of mispredicted near RET branch instructions retired.
452 The number of mispredicted near CALL branch instructions retired.
455 The number of mispredicted near indirect CALL branch instructions
459 The number of mispredicted near relative CALL branch instructions
463 The number of mispredicted branch instructions retired that were
467 The number of cycles when no uops are allocated and the ROB is full
471 The number of cycles when no uops are allocated and a RATstall is
475 The number of cycles when the front-end does not provide any
479 The number of cycles when the front-end does not provide any
483 The number of cycles the allocation pipe line stalled due to
487 The number of cycles that the allocation pipe line stalled due
491 The number of cycles the divider is busy.
494 The number of baclears for any type of branch.
497 The number of baclears for return branches.
500 The number of baclears for conditional branches.
503 The number of times the MSROM starts a flow of UOPS.