Lines Matching +full:event +full:-

16 .\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
59 .%B "Intel 64 and IA-32 Intel(R) Architecture Software Developer's Manual"
61 .%N "Order Number 325462-050US"
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
84 .Ss Event Qualifiers
85 Event specifiers for these PMCs support the following common
87 .Bl -tag -width indent
95 Configure the PMC to count the number of de-asserted to asserted
121 Events that require core-specificity to be specified use a
127 .Bl -tag -width indent
129 Measure event conditions on all cores.
131 Measure event conditions on this core.
143 .Bl -tag -width indent
159 .Bl -tag -width "exclude"
177 .Bl -tag -width indent
199 .Bl -tag -width indent
215 .Bl -tag -width indent
223 .Ss Event Specifiers (Programmable PMCs)
225 .Bl -tag -width indent
227 .Pq Event 03H , Umask 01H
232 .Pq Event 03H , Umask 02H
237 .Pq Event 03H , Umask 04H
241 .Pq Event 03H , Umask 08H
245 .Pq Event 03H , Umask 10H
251 .Pq Event 03H , Umask 20H
255 .Pq Event 03H , Umask 40H
258 .Pq Event 03H , Umask 80H
261 .Pq Event 04H , Umask 01H
266 .Pq Event 04H , Umask 02H
267 The number of load micro-ops retired that hit L2.
269 .Pq Event 04H , Umask 04H
270 The number of load micro-ops retired that missed L2.
272 .Pq Event 04H , Umask 08H
275 .Pq Event 04H , Umask 10H
278 .Pq Event 04H , Umask 20H
282 .Pq Event 04H , Umask 40H
285 .Pq Event 04H , Umask 80H
288 .Pq Event 05H , Umask 01H
289 Every cycle when a D-side (walks due to a load) page walk is in progress.
291 page-walks.
295 .Pq Event 05H , Umask 02H
296 Every cycle when a I-side (walks due to an instruction fetch) page walk is in
299 page-walks.
301 .Pq Event 05H , Umask 03H
307 .Pq Event 2EH , Umask 41H
312 .Pq Event 2EH , Umask 4FH
317 .Pq Event 30H , Umask 00H
321 The XQ may reject transactions from the L2Q (non-cacheable
322 requests), BBS (L2 misses) and WOB (L2 write-back victims)
324 .Pq Event 31H , Umask 00H
335 event).
337 .Pq Event 3CH , Umask 00H
341 For this reason this event may have a changing ratio with regards to time.
343 .Pq Event 3CH , Umask 01H
347 This event is not affected by core frequency changes but counts as if the core
350 .Pq Event 80H , Umask 01H
353 .Pq Event 80H , Umask 02H
360 .Pq Event 80H , Umask 03H
363 .Pq Event B6H , Umask 04H
368 .Pq Event B7H , Umask 01H
371 .Pq Event B7H , Umask 02H
374 .Pq Event C0H , Umask 00H
376 For instructions that consist of multiple micro-ops, this event counts the
377 retirement of the last micro-op of the instruction.
381 .Pq Event C2H , Umask 01H
382 The number of micro-ops retired that were supplied from MSROM.
384 .Pq Event C2H , Umask 10H
385 The number of micro-ops retired.
387 .Pq Event C3H , Umask 01H
389 Self-modifying code causes a severe penalty in all Intel
392 .Pq Event C3H , Umask 02H
396 .Pq Event C3H , Umask 04H
400 .Pq Event C3H , Umask 08H
404 .Pq Event C4H , Umask 00H
407 .Pq Event C4H , Umask 7EH
411 .Pq Event C4H , Umask BFH
414 .Pq Event C4H , Umask EBH
418 .Pq Event C4H , Umask F7H
421 .Pq Event C4H , Umask F9H
424 .Pq Event C4H , Umask FBH
427 .Pq Event C4H , Umask FDH
430 .Pq Event C4H , Umask FEH
434 .Pq Event C5H , Umask 00H
437 .Pq Event C5H , Umask 7EH
441 .Pq Event C5H , Umask BFH
444 .Pq Event C5H , Umask EBH
448 .Pq Event C5H , Umask F7H
451 .Pq Event C5H , Umask F9H
454 .Pq Event C5H , Umask FBH
458 .Pq Event C5H , Umask FDH
462 .Pq Event C5H , Umask FEH
466 .Pq Event CAH , Umask 01H
470 .Pq Event CAH , Umask 20H
474 .Pq Event CAH , Umask 3FH
475 The number of cycles when the front-end does not provide any
478 .Pq Event CAH , Umask 50H
479 The number of cycles when the front-end does not provide any
482 .Pq Event CBH , Umask 01H
486 .Pq Event CBH , Umask 1FH
490 .Pq Event CDH , Umask 01H
493 .Pq Event E6H , Umask 01H
496 .Pq Event E6H , Umask 08H
499 .Pq Event E6H , Umask 10H
502 .Pq Event E7H , Umask 01H)
523 .An -nosplit