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40 CPUs contain PMCs conforming to version 3 of the
43 These CPUs contains two classes of PMCs:
48 Programmable counters that may be configured to count one of a defined
49 set of hardware events.
52 The number of PMCs available in each class and their widths need to be
90 Configure the PMC to increment only if the number of configured
94 Configure the PMC to count the number of de-asserted to asserted
95 transitions of the conditions expressed by the other qualifiers.
97 condition becomes true, irrespective of the number of clocks during
100 Invert the sense of comparison when the
102 qualifier is present, making the counter increment when the number of
114 If neither of the
125 is one of:
141 is one of:
157 is one of:
175 contains one or more of the following letters:
195 comprises of the following keywords separated by
213 comprises the one of the following keywords:
227 The number of times the front end is resteered.
230 The number of byte sequences mistakenly detected as taken branch
234 The number of branch instructions that were mispredicted when
238 The number of mispredicted
243 The number of
248 The number of conditional branches executed, but not necessarily retired.
251 The number of mispredicted conditional branches executed.
254 The number of indirect
259 The number of indirect branch instructions executed.
262 The number of mispredicted indirect branch instructions executed.
265 The number of branch instructions decoded.
268 The number of branches executed, but not necessarily retired.
272 The number of branch instructions retired.
276 The number of branch instructions retired that were mispredicted.
280 The number of mispredicted branch instructions retired.
284 The number of not taken branch instructions retired that were
291 The number of not taken branch instructions retired that were
295 The number of taken branch instructions retired that were correctly
299 The number of taken branch instructions retired.
302 The number of mispredicted branch instructions that were executed.
305 The number of mispredicted
310 The number of
315 The number of
320 The number of branch predicted taken with bubble 1.
323 The number of branch predicted taken with bubble 2.
326 The number of cycles during which the core did not have any pending
330 The number of Bus Not Ready signals asserted on the bus.
334 The number of bus cycles during which the processor is receiving data.
338 The number of bus cycles during which the Data Ready signal is asserted
343 The number of bus cycles during which the processor drives the
349 The number of bus cycles during which the processor drives the
355 The number of core cycles during which I/O requests wait in the bus
362 The number of bus cycles during which the
371 The number of pending full cache line read transactions on the bus
379 The number of partial bus transactions.
385 The number of instruction fetch full cache line bus transactions.
391 The number of invalidate bus transactions.
397 The number of partial write bus transactions.
403 The number of deferred bus transactions.
409 The number of burst transactions.
415 The number of memory bus transactions.
421 The number of bus transactions of any kind.
427 The number of burst read transactions.
433 The number of completed I/O bus transactions due to
443 The number of Read For Ownership bus transactions.
456 The number of times the L1 data cache is snooped by the other core in
461 The number of bus cycles when the core is not in the halt state.
466 The number of core cycles while the core is not in a halt state.
470 The number of bus cycles during which the core remains unhalted and
474 The number of cycles the divider is busy.
477 The number of cycles during which interrupts are disabled.
480 The number of cycles during which there were pending interrupts while
484 The number of cycles for which an instruction fetch stalls.
487 The number of memory access that missed the Data TLB
490 The number of loads that missed the Data TLB.
493 The number of stores that missed the Data TLB.
496 The number of loads that missed the UTLB.
499 The number of floating point operations that used data immediately
503 The number of delayed bypass penalty cycles that a load operation incurred.
506 The number of times SIMD operations use data immediately after data,
510 The number of divide operations executed.
514 The number of divide operations retired.
517 The number of divide operations executed.
520 The number of Data TLB misses, including misses that result from
524 The number of level 0 DTLB misses due to load operations.
527 The number of Data TLB misses due to load operations.
530 The number of Data TLB misses due to store operations.
533 The number of Enhanced Intel SpeedStep Technology transitions.
536 The number of automatic additions to the
541 The number of times the
554 The number of snoop responses to bus transactions.
557 The number of floating point operations executed that needed
561 The number of floating point operations retired that needed
565 The number of floating point computational micro-ops executed.
569 The number of transitions from MMX instructions to floating point
573 The number of transitions from floating point instructions to MMX
577 The number of hardware interrupts received.
580 The number of instruction fetches.
583 The number of instruction fetches that miss the instruction cache.
586 The number of cycles the divider is busy and no other execution unit
591 The number of cycles the instruction length decoder stalled due to a
595 The number of cycles during which the instruction queue is full.
599 The number of instructions retired.
603 The number of instructions retired that contained a load operation.
606 The number of instructions retired that did not contain a load or a
610 The number of instructions retired that contained a store operation.
613 The number of ITLB flushes.
616 The number of instruction fetches from large pages that miss the
620 The number of instruction fetches from both large and small pages that
624 The number of instruction fetches from small pages that miss the ITLB.
627 The number of retired instructions that missed the ITLB when they were
631 The number of references to L1 data cache counting loads and stores of
635 The number of data reads and writes to cacheable memory.
638 The number of locked reads from cacheable memory.
641 The number of cycles during which any cache line is locked by any
645 The number of data reads from cacheable memory.
648 The number of data writes to cacheable memory.
651 The number of modified cache lines evicted from L1 data cache.
654 The number of modified lines allocated in L1 data cache.
657 The total number of outstanding L1 data cache misses at any clock.
660 The number of times L1 data cache requested to prefetch a data cache
664 The number of lines brought into L1 data cache.
667 The number of load operations that span two cache lines.
670 The number of store operations that span two cache lines.
673 The number of instruction fetch unit misses.
676 The number of instruction fetches.
679 The number of cycles that the L2 address bus is in use.
682 The number of core cycles during which the L2 data bus is busy
689 The number of instruction cache line requests from the instruction
697 The number of L2 cache read requests from L1 cache and L2
704 The number of cache lines allocated in L2 cache.
710 The number of L2 cache lines evicted.
716 The number of locked accesses to cache lines that miss L1 data
720 The number of L2 cache line modifications.
726 The number of modified lines evicted from L2 cache.
729 The number of cycles during which no L2 cache requests were pending
737 The number of L2 cache requests that were rejected.
744 The number of completed L2 cache requests.
748 The number of completed L2 cache demand requests from this core that
754 The number of completed L2 cache demand requests from this core.
760 The number of store operations that miss the L1 cache and request data
764 The number of loads blocked by the L1 data cache.
767 The number of loads that partially overlap an earlier store or are
771 The number of loads blocked by preceding stores whose address is yet
775 The number of loads blocked by preceding stores to the same address
779 The number of load operations that were blocked until retirement.
782 The number of load operations that conflicted with an prefetch to the
786 The number of times a program writes to a code section.
789 The number of times the execution pipeline was restarted due to a
793 The number of instructions decoded.
796 The number of complex instructions decoded.
799 The number of cycles during which memory disambiguation misprediction
803 The number of load operations that were successfully disambiguated.
806 The number of retired load operations that missed the DTLB.
809 The number of retired load operations that miss L2 cache.
812 The number of retired load operations that hit L2 cache.
815 The number of load operations that missed L2 cache and that caused a
819 The number of multiply operations executed.
823 The number of multiply operations retired.
826 The number of multiply operations executed.
829 The number of page walks executed due to an ITLB or DTLB miss.
833 The number of cycles spent in a page walk caused by an ITLB or DTLB
837 The number of downward prefetches issued from the Data Prefetch Logic
841 The number of upward prefetches issued from the Data Prefetch Logic
845 The number of
850 The number of
855 The number of
862 The number of stall cycles due to any of
870 The number of cycles execution stalled due to a flag register induced
874 The number of times the floating point status word was written.
877 The number of cycles of added instruction execution latency due to the
878 use of a register that was partially written by previous instructions.
881 The number of cycles when ROB read port stalls occurred.
884 The number of cycles during which any resource related stall
888 The number of cycles stalled due to branch misprediction.
891 The number of cycles stalled due to writing the floating point control
895 The number of cycles during which the number of loads and stores in
899 The number of cycles when the reorder buffer was full.
902 The number of cycles during which the RS was full.
905 The number of micro-ops dispatched for execution.
908 The number of cycles micro-ops were dispatched for execution on port
912 The number of cycles micro-ops were dispatched for execution on port
916 The number of cycles micro-ops were dispatched for execution on port
920 The number of cycles micro-ops were dispatched for execution on port
924 The number of cycles micro-ops were dispatched for execution on port
928 The number of cycles micro-ops were dispatched for execution on port
932 The number of cycles while the store buffer is draining.
935 The number of segment register loads.
938 The number of times the any segment register was renamed.
941 The number of times the
946 The number of times the
951 The number of times the
956 The number of times the
961 The number of stalls due to lack of resource to rename any segment
965 The number of stalls due to lack of renaming resources for the
970 The number of stalls due to lack of renaming resources for the
975 The number of stalls due to lack of renaming resources for the
980 The number of stalls due to lack of renaming resources for the
988 Then number of computational SSE2 packed double precision instructions
992 Then number of computational SSE2 packed single precision instructions
996 Then number of computational SSE2 scalar double precision instructions
1000 Then number of computational SSE2 scalar single precision instructions
1004 The number of retired SIMD instructions that use MMX registers.
1007 The number of streaming SIMD instructions retired.
1010 The number of SSE2 packed double precision instructions retired.
1013 The number of SSE packed single precision instructions retired.
1016 The number of SSE2 scalar double precision instructions retired.
1019 The number of SSE scalar single precision instructions retired.
1022 The number of SSE2 vector instructions retired.
1025 The number of saturated arithmetic SIMD instructions retired.
1028 The number of SIMD saturated arithmetic micro-ops retired.
1031 The number of SIMD saturated arithmetic micro-ops executed.
1034 The number of SIMD micro-ops retired.
1037 The number of SIMD micro-ops executed.
1040 The number of SIMD packed arithmetic micro-ops executed.
1043 The number of SIMD packed arithmetic micro-ops executed.
1046 The number of SIMD packed logical micro-ops executed.
1049 The number of SIMD packed logical micro-ops executed.
1052 The number of SIMD packed multiply micro-ops retired.
1055 The number of SIMD packed multiply micro-ops executed.
1058 The number of SIMD pack micro-ops retired.
1061 The number of SIMD pack micro-ops executed.
1064 The number of SIMD packed shift micro-ops retired.
1067 The number of SIMD packed shift micro-ops executed.
1070 The number of SIMD unpack micro-ops executed.
1073 The number of SIMD unpack micro-ops executed.
1079 The number of times the bus stalled for snoops.
1083 The number of
1088 The number of times SSE non-temporal store instructions were executed.
1091 The number of times the
1096 The number of times the
1101 The number of times the
1106 The number of cycles while a store was waiting for another store to be
1110 The number of cycles while a store was blocked due to a conflict with
1114 The number of times stored data was forwarded directly to a load.
1117 The number of thermal trips.
1120 The number of micro-ops retired that fused a load with another
1124 The number of store address calculations that fused into one micro-op.
1127 The number of times retired instruction pairs were fused into one
1131 The number of fused micro-ops retired.
1134 The number of non-fused micro-ops retired.
1137 The number of micro-ops retired.
1140 The number of x87 floating-point computational micro-ops retired.
1143 The number of x87 floating-point computational micro-ops executed.
1146 The number of floating point computational instructions retired.
1149 The number of