Lines Matching +full:lock +full:- +full:latency +full:- +full:ns

44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual"
60 .%N "Order Number 253669-027US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
89 .It Li cmask= Ns Ar value
94 Configure the PMC to count the number of de-asserted to asserted
120 Events that require core-specificity to be specified use a
122 .Dq Li core= Ns Ar core ,
126 .Bl -tag -width indent
138 .Dq Li agent= Ns agent ,
142 .Bl -tag -width indent
154 .Dq Li prefetch= Ns Ar prefetch ,
158 .Bl -tag -width "exclude"
172 .Dq Li cachestate= Ns Ar state ,
176 .Bl -tag -width indent
192 .Dq Li snoopresponse= Ns Ar response ,
198 .Bl -tag -width indent
210 .Dq Li snooptype= Ns Ar type ,
214 .Bl -tag -width indent
224 .Bl -tag -width indent
324 .It Li BUSQ_EMPTY Op ,core= Ns Ar core
328 .It Li BUS_BNR_DRV Op ,agent= Ns Ar agent
331 This event is thread-independent.
332 .It Li BUS_DATA_RCV Op ,core= Ns Ar core
335 This event is thread-independent.
336 .It Li BUS_DRDY_CLOCKS Op ,agent= Ns Ar agent
340 This event is thread-independent.
341 .It Li BUS_HIT_DRV Op ,agent= Ns Ar agent
346 This event is thread-independent.
347 .It Li BUS_HITM_DRV Op ,agent= Ns Ar agent
352 This event is thread-independent.
353 .It Li BUS_IO_WAIT Op ,core= Ns Ar core
358 .Op ,agent= Ns Ar agent
359 .Op ,core= Ns Ar core
363 .Li LOCK
367 .Op ,agent= Ns Ar agent
368 .Op ,core= Ns Ar core
375 .Op ,agent= Ns Ar agent
376 .Op ,core= Ns Ar core
381 .Op ,agent= Ns Ar agent
382 .Op ,core= Ns Ar core
387 .Op ,agent= Ns Ar agent
388 .Op ,core= Ns Ar core
393 .Op ,agent= Ns Ar agent
394 .Op ,core= Ns Ar core
399 .Op ,agent= Ns Ar agent
400 .Op ,core= Ns Ar core
405 .Op ,agent= Ns Ar agent
406 .Op ,core= Ns Ar core
411 .Op ,agent= Ns Ar agent
412 .Op ,core= Ns Ar core
417 .Op ,agent= Ns Ar agent
418 .Op ,core= Ns Ar core
423 .Op ,agent= Ns Ar agent
424 .Op ,core= Ns Ar core
429 .Op ,agent= Ns Ar agent
430 .Op ,core= Ns Ar core
439 .Op ,agent= Ns Ar agent
440 .Op ,core= Ns Ar core
445 .Op ,agent= Ns Ar agent
446 .Op ,core= Ns Ar core
449 The number explicit write-back bus transactions due to dirty line
452 .Op ,core= Ns Ar core
453 .Op ,snooptype= Ns Ar snoop
507 was generated by a non-SIMD execution unit.
550 .Op ,agent= Ns Ar agent
551 .Op ,snoopresponse= Ns Ar response
565 The number of floating point computational micro-ops executed.
636 .It Li L1D_CACHE_LOCK Op ,cachestate= Ns Ar state
677 .It Li L2_ADS Op ,core= Ns core
680 .It Li L2_DBUS_BUSY_RD Op ,core= Ns core
685 .Op ,cachestate= Ns Ar state
686 .Op ,core= Ns Ar core
692 .Op ,cachestate= Ns Ar state
693 .Op ,core= Ns Ar core
694 .Op ,prefetch= Ns Ar prefetch
700 .Op ,core= Ns Ar core
701 .Op ,prefetch= Ns Ar prefetch
706 .Op ,core= Ns Ar core
707 .Op ,prefetch= Ns Ar prefetch
712 .Op ,cachestate= Ns Ar state
713 .Op ,core= Ns Ar core
718 .It Li L2_M_LINES_IN Op ,core= Ns Ar core
722 .Op ,core= Ns Ar core
723 .Op ,prefetch= Ns Ar prefetch
727 .It Li L2_NO_REQ Op ,core= Ns Ar core
732 .Op ,cachestate= Ns Ar state
733 .Op ,core= Ns Ar core
734 .Op ,prefetch= Ns Ar prefetch
739 .Op ,cachestate= Ns Ar state
740 .Op ,core= Ns Ar core
741 .Op ,prefetch= Ns Ar prefetch
756 .Op ,cachestate= Ns Ar state
757 .Op ,core= Ns Ar core
877 The number of cycles of added instruction execution latency due to the
905 The number of micro-ops dispatched for execution.
908 The number of cycles micro-ops were dispatched for execution on port
912 The number of cycles micro-ops were dispatched for execution on port
916 The number of cycles micro-ops were dispatched for execution on port
920 The number of cycles micro-ops were dispatched for execution on port
924 The number of cycles micro-ops were dispatched for execution on port
928 The number of cycles micro-ops were dispatched for execution on port
1028 The number of SIMD saturated arithmetic micro-ops retired.
1031 The number of SIMD saturated arithmetic micro-ops executed.
1034 The number of SIMD micro-ops retired.
1037 The number of SIMD micro-ops executed.
1040 The number of SIMD packed arithmetic micro-ops executed.
1043 The number of SIMD packed arithmetic micro-ops executed.
1046 The number of SIMD packed logical micro-ops executed.
1049 The number of SIMD packed logical micro-ops executed.
1052 The number of SIMD packed multiply micro-ops retired.
1055 The number of SIMD packed multiply micro-ops executed.
1058 The number of SIMD pack micro-ops retired.
1061 The number of SIMD pack micro-ops executed.
1064 The number of SIMD packed shift micro-ops retired.
1067 The number of SIMD packed shift micro-ops executed.
1070 The number of SIMD unpack micro-ops executed.
1073 The number of SIMD unpack micro-ops executed.
1075 .Op ,agent= Ns Ar agent
1076 .Op ,core= Ns Ar core
1080 This event is thread-independent.
1088 The number of times SSE non-temporal store instructions were executed.
1120 The number of micro-ops retired that fused a load with another
1124 The number of store address calculations that fused into one micro-op.
1128 micro-op.
1131 The number of fused micro-ops retired.
1134 The number of non-fused micro-ops retired.
1137 The number of micro-ops retired.
1140 The number of x87 floating-point computational micro-ops retired.
1143 The number of x87 floating-point computational micro-ops executed.
1154 The following table shows the mapping between the PMC-independent
1158 .Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class"
1161 .It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP
1162 .It Li ic-misses Ta Li ICACHE.MISSES Ta Li PMC_CLASS_IAP
1165 .It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF