Lines Matching full:during
97 condition becomes true, irrespective of the number of clocks during
326 The number of cycles during which the core did not have any pending
334 The number of bus cycles during which the processor is receiving data.
338 The number of bus cycles during which the Data Ready signal is asserted
343 The number of bus cycles during which the processor drives the
349 The number of bus cycles during which the processor drives the
355 The number of core cycles during which I/O requests wait in the bus
362 The number of bus cycles during which the
470 The number of bus cycles during which the core remains unhalted and
477 The number of cycles during which interrupts are disabled.
480 The number of cycles during which there were pending interrupts while
595 The number of cycles during which the instruction queue is full.
641 The number of cycles during which any cache line is locked by any
682 The number of core cycles during which the L2 data bus is busy
729 The number of cycles during which no L2 cache requests were pending
799 The number of cycles during which memory disambiguation misprediction
884 The number of cycles during which any resource related stall
895 The number of cycles during which the number of loads and stores in
902 The number of cycles during which the RS was full.