Lines Matching full:count

72 .It Li count= Ns Ar value
77 Configure the counter to only count negated-to-asserted transitions
84 .Dq Li count
88 .Dq Li count
96 Configure the PMC to count events happening at privilege level 0.
98 Configure the PMC to count events occurring at privilege levels 1, 2
112 Count the number of clock cycles when the CPU is not in the HLT or
116 Count fill requests that missed in the L2 cache.
125 Count data cache fill requests.
127 Count instruction cache fill requests.
129 Count TLB reloads.
132 The default is to count all types of requests.
144 Count lines written into L2 cache due to victim writebacks from the
147 Count writebacks of dirty lines from L2 to the system.
151 Count internally generated requests to the L2 cache.
160 Count cancelled requests.
162 Count data cache fill requests.
164 Count instruction cache fill requests.
166 Count tag snoop requests.
168 Count TLB reloads.
171 The default is to count all types of requests.
174 Count data cache accesses including microcode scratch pad accesses.
177 Count data cache copyback operations.
186 Count operations for lines in the
190 Count operations for lines in the
194 Count operations for lines in the
198 Count operations for lines in the
202 Count operations for lines in the
207 The default is to count operations for lines in all the
211 Count data cache accesses by lock instructions.
222 Count data cache accesses by lock instructions.
224 Count data cache misses by lock instructions.
227 The default is to count all accesses.
230 Count the number of dispatched prefetch instructions.
239 Count load operations.
241 Count non-temporal operations.
243 Count store operations.
246 The default is to count all operations.
249 Count L1 DTLB misses that are L2 DTLB hits.
252 Count L1 DTLB misses that are also misses in the L2 DTLB.
255 Count microarchitectural early cancels of data cache accesses.
258 Count microarchitectural late cancels of data cache accesses.
261 Count misaligned data references.
264 Count data cache misses.
267 Count one bit ECC errors found by the scrubber.
276 Count scrubber detected errors.
278 Count piggyback scrubber errors.
281 The default is to count both kinds of errors.
284 Count data cache refills from L2 cache.
293 Count operations for lines in the
297 Count operations for lines in the
301 Count operations for lines in the
305 Count operations for lines in the
309 Count operations for lines in the
314 The default is to count operations for lines in all the
318 Count data cache refills from system memory.
327 Count operations for lines in the
331 Count operations for lines in the
335 Count operations for lines in the
339 Count operations for lines in the
343 Count operations for lines in the
348 The default is to count operations for lines in all the
352 Count cycles when no FPU ops were retired.
356 Count dispatched FPU ops that use the fast flag interface.
360 Count the number of dispatched FPU ops.
370 Count add pipe ops excluding junk ops.
372 Count junk ops in the add pipe.
374 Count multiply pipe ops excluding junk ops.
376 Count junk ops in the multiply pipe.
378 Count store pipe ops excluding junk ops
380 Count junk ops in the store pipe.
383 The default is to count all types of ops.
386 Count cycles when there was nothing to dispatch (i.e., the decoder
390 Count dispatch stalls for segment loads.
393 Count dispatch stalls for serialization.
396 Count dispatch stalls from branch abort to retiral.
399 Count dispatch stalls when the FPU is full.
402 Count dispatch stalls when the load/store unit is full.
405 Count dispatch stalls when the reorder buffer is full.
408 Count dispatch stalls when reservation stations are full.
411 Count dispatch stalls when a far control transfer or a resync branch
415 Count dispatch stalls when waiting for all to be quiet.
419 Count all dispatch stalls.
422 Count FPU exceptions.
432 Count SSE and x87 microtraps.
434 Count SSE reclass microfaults
436 Count SSE retype microfaults
438 Count x87 reclass microfaults.
441 The default is to count all types of exceptions.
444 Count cycles when interrupts were masked (by CPU RFLAGS field IF was zero).
447 Count cycles while interrupts were masked while pending (i.e., cycles
451 Count the number of breakpoints for DR0.
454 Count the number of breakpoints for DR1.
457 Count the number of breakpoints for DR2.
460 Count the number of breakpoints for DR3.
463 Count retired branches including exceptions and interrupts.
466 Count mispredicted retired branches.
469 Count retired far control transfers (which are always mispredicted).
472 Count retired fastpath double op instructions.
482 Count instructions with the low op in position 0.
484 Count instructions with the low op in position 1.
486 Count instructions with the low op in position 2.
489 The default is to count all types of instructions.
492 Count retired FPU instructions.
502 Count MMX and 3DNow!\& instructions.
504 Count packed SSE and SSE2 instructions.
506 Count scalar SSE and SSE2 instructions
508 Count x87 instructions.
511 The default is to count all types of instructions.
514 Count retired near returns.
517 Count mispredicted near returns.
520 Count retired resyncs (non-control transfer branches).
523 Count retired taken branches.
526 Count retired taken branches that were mispredicted.
529 Count retired taken branches that were mispredicted only due to an
533 Count retired taken hardware interrupts.
536 Count retired uops.
539 Count retired x86 instructions including exceptions and interrupts.
542 Count instruction cache fetches.
545 Count cycles in stalls due to instruction fetch.
548 Count L1 ITLB misses that are L2 ITLB hits.
551 Count ITLB misses that miss in both L1 and L2 ITLBs.
554 Count microarchitectural resyncs caused by snoops.
557 Count instruction cache misses.
560 Count instruction cache refills from L2 cache.
563 Count instruction cache refills from system memory.
566 Count hits to the return stack.
569 Count overflows of the return stack.
572 Count load/store buffer2 full events.
575 Count locked operations.
580 Count the number of cycles in the lock request/grant stage.
582 Count the number of cycles a lock takes to complete once it is
585 Count the number of lock instructions executed.
588 The default is to count the number of lock instructions executed.
591 Count microarchitectural late cancels of operations in the load/store
595 Count microarchitectural resyncs caused by self-modifying code.
598 Count microarchitectural resyncs caused by snoops.
601 Count retired CFLUSH instructions.
604 Count retired CPUID instructions.
607 Count segment register loads.
615 Count CS register loads.
617 Count DS register loads.
619 Count ES register loads.
621 Count FS register loads.
623 Count GS register loads.
625 .\" Count HS register loads.
628 Count SS register loads.
631 The default is to count all types of loads.
636 Count events on the HyperTransport(tm) buses.
645 Count buffer release messages sent.
647 Count command messages sent.
649 Count data messages sent.
651 Count nop messages sent.
654 The default is to count all types of messages.
657 Count memory controller bypass counter saturation events.
666 Count DRAM controller interface bypass.
668 Count DRAM controller queue bypass.
670 Count memory controller high priority bypasses.
672 Count memory controller low priority bypasses.
676 Count memory controller DRAM command slots missed (in MemClks).
679 Count memory controller page access events.
688 Count page conflicts.
690 Count page hits.
692 Count page misses.
695 The default is to count all types of events.
698 Count memory control page table overflow events.
701 Count memory control turnaround events.
711 Count DIMM turnarounds.
713 Count read to write turnarounds.
715 Count write to read turnarounds.
718 The default is to count all types of events.
721 Count probe events.
730 Count all probe hits.
732 Count probe hits without memory cancels.
734 Count probe hits with memory cancels.
736 Count probe misses.
740 Count sized commands issued.
757 The default is to count all types of commands.