Lines Matching +full:reserved +full:- +full:cpu +full:- +full:vectors

5 OPENSSL_ia32cap - the x86[_64] processor capabilities vector
15 stored internally as ten 32-bit capability vectors and for simplicity
16 represented logically below as five 64-bit vectors. This logical
20 Upon toolkit initialization, the capability vectors are populated through
23 initialization is complete, populated vectors are then used to choose
39 =item bit #0+4 denoting presence of Time-Stamp Counter;
43 =item bit #0+20, reserved by Intel, is used to choose among RC4 code paths;
56 =item bit #0+30, reserved by Intel, denotes specifically Intel CPUs;
62 =item bit #0+43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
66 =item bit #0+57 denoting AES-NI instruction set extension;
124 =item bit #128+15 denoting availability of Hybrid CPU;
134 =item bit #128+55 denoting availability of AVX-IFMA extension;
174 The variable consists of a series of 64-bit numbers representing each
175 of the logical vectors (LV) described above. Each value is delimited by a 'B<:>'.
180 Used in this form, each non-null logical vector will *overwrite* the entire corresponding
185 To illustrate, the following will zero all capability bits in logical vectors 1 and further
186 (disable all post-AVX extensions):
190 The following will zero all capability bits in logical vectors 2 and further:
207 the rest of the logical vectors unchanged:
217 the decision on whether or not expensive countermeasures against cache-timing attacks
226 Copyright 2004-2021 The OpenSSL Project Authors. All Rights Reserved.