Lines Matching +full:isa +full:- +full:extensions

5 OPENSSL_ia32cap - the x86[_64] processor capabilities vector
13 OpenSSL supports a range of x86[_64] instruction set extensions and
14 features. These extensions are denoted by individual bits or groups of bits
15 stored internally as ten 32-bit capability vectors and for simplicity
16 represented logically below as five 64-bit vectors. This logical
28 Instruction Set Extensions Programming Reference, and the AMD64 Architecture
39 =item bit #0+4 denoting presence of Time-Stamp Counter;
62 =item bit #0+43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
66 =item bit #0+57 denoting AES-NI instruction set extension;
134 =item bit #128+55 denoting availability of AVX-IFMA extension;
146 =item bit #192+19 denoting availability of AVX10 Converged Vector ISA extension;
160 =item bits #256+32+[0:7] denoting AVX10 Converged Vector ISA Version (8 bits);
174 The variable consists of a series of 64-bit numbers representing each
180 Used in this form, each non-null logical vector will *overwrite* the entire corresponding
186 (disable all post-AVX extensions):
197 A more likely usage scenario would be to disable specific instruction set extensions.
198 The 'B<~>' character is used to specify a bit mask of the extensions to be disabled for
201 To illustrate, the following will disable AVX2 code paths and further extensions:
206 extensions and therefore any code paths using those extensions but leave
217 the decision on whether or not expensive countermeasures against cache-timing attacks
226 Copyright 2004-2021 The OpenSSL Project Authors. All Rights Reserved.