Lines Matching +full:extended +full:- +full:range +full:- +full:enable

5 OPENSSL_ia32cap - the x86[_64] processor capabilities vector
13 OpenSSL supports a range of x86[_64] instruction set extensions. These
19 range of processors. For the moment of this writing following bits are
24 =item bit #4 denoting presence of Time-Stamp Counter.
47 =item bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
51 =item bit #57 denoting AES-NI instruction set extension;
64 For example, in 32-bit application context clearing bit #26 at run-time
65 disables high-performance SSE2 code present in the crypto library, while
66 clearing bit #24 disables SSE2 code operating on 128-bit XMM register
69 enable XMM registers. Historically address of the capability vector copy
76 effect. Alternatively you can reconfigure the toolkit with no-sse2
83 on whether or not expensive countermeasures against cache-timing attacks
86 The capability vector is further extended with EBX value returned by
121 To control this extended capability word use C<:> as delimiter when
123 C<:~0x20> would disable AVX2 code paths, and C<:0> - all post-AVX
132 Copyright 2004-2021 The OpenSSL Project Authors. All Rights Reserved.