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33 The following are notable capability bits from logical vector 0 (LV0)
34 resulting from the following execution of CPUID.(EAX=01H).EDX and
81 The following are notable capability bits from logical vector 1 (LV1)
82 resulting from the following execution of CPUID.(EAX=07H,ECX=0H).EBX and
118 The following are notable capability bits from logical vector 2 (LV2)
119 resulting from the following execution of CPUID.(EAX=07H,ECX=0H).EDX and
140 The following are notable capability bits from logical vector 3 (LV3)
141 resulting from the following execution of CPUID.(EAX=07H,ECX=1H).EDX and
154 The following are notable capability bits from logical vector 4 (LV4)
155 resulting from the following execution of CPUID.(EAX=07H,ECX=1H).ECX and
185 To illustrate, the following will zero all capability bits in logical vectors 1 and further
190 The following will zero all capability bits in logical vectors 2 and further:
194 The following will zero all capability bits only in logical vector 1:
201 To illustrate, the following will disable AVX2 code paths and further extensions:
205 The following will disable AESNI (LV0 bit 57) and VAES (LV1 bit 41)