Lines Matching +full:0 +full:x49c
38 #define MYPF_BASE 0x1b000
41 #define PF0_BASE 0x1e000
44 #define PF_STRIDE 0x400
48 #define MYPORT_BASE 0x1c000
51 #define PORT0_BASE 0x20000
54 #define PORT_STRIDE 0x2000
68 #define SGE_PF_KDOORBELL_A 0x0
77 #define PIDX_S 0
80 #define SGE_VF_KDOORBELL_A 0x0
86 #define PIDX_T5_S 0
87 #define PIDX_T5_M 0x1fffU
91 #define SGE_PF_GTS_A 0x4
102 #define CIDXINC_S 0
103 #define CIDXINC_M 0xfffU
106 #define SGE_CONTROL_A 0x1008
107 #define SGE_CONTROL2_A 0x1124
118 #define PKTSHIFT_M 0x7U
126 #define INGPADBOUNDARY_M 0x7U
134 #define INGPACKBOUNDARY_M 0x7U
143 #define SGE_DBVFIFO_BADDR_A 0x1138
146 #define DBVFIFO_SIZE_M 0xfffU
149 #define T6_DBVFIFO_SIZE_S 0
150 #define T6_DBVFIFO_SIZE_M 0x1fffU
153 #define GLOBALENABLE_S 0
157 #define SGE_HOST_PAGE_SIZE_A 0x100c
160 #define HOSTPAGESIZEPF7_M 0xfU
165 #define HOSTPAGESIZEPF6_M 0xfU
170 #define HOSTPAGESIZEPF5_M 0xfU
175 #define HOSTPAGESIZEPF4_M 0xfU
180 #define HOSTPAGESIZEPF3_M 0xfU
185 #define HOSTPAGESIZEPF2_M 0xfU
190 #define HOSTPAGESIZEPF1_M 0xfU
194 #define HOSTPAGESIZEPF0_S 0
195 #define HOSTPAGESIZEPF0_M 0xfU
199 #define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010
200 #define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014
204 #define QUEUESPERPAGEPF0_S 0
205 #define QUEUESPERPAGEPF0_M 0xfU
209 #define SGE_INT_CAUSE1_A 0x1024
210 #define SGE_INT_CAUSE2_A 0x1030
211 #define SGE_INT_CAUSE3_A 0x103c
309 #define SGE_INT_ENABLE3_A 0x1040
310 #define SGE_FL_BUFFER_SIZE0_A 0x1044
311 #define SGE_FL_BUFFER_SIZE1_A 0x1048
312 #define SGE_FL_BUFFER_SIZE2_A 0x104c
313 #define SGE_FL_BUFFER_SIZE3_A 0x1050
314 #define SGE_FL_BUFFER_SIZE4_A 0x1054
315 #define SGE_FL_BUFFER_SIZE5_A 0x1058
316 #define SGE_FL_BUFFER_SIZE6_A 0x105c
317 #define SGE_FL_BUFFER_SIZE7_A 0x1060
318 #define SGE_FL_BUFFER_SIZE8_A 0x1064
320 #define SGE_IMSG_CTXT_BADDR_A 0x1088
321 #define SGE_FLM_CACHE_BADDR_A 0x108c
322 #define SGE_INGRESS_RX_THRESHOLD_A 0x10a0
325 #define THRESHOLD_0_M 0x3fU
330 #define THRESHOLD_1_M 0x3fU
335 #define THRESHOLD_2_M 0x3fU
339 #define THRESHOLD_3_S 0
340 #define THRESHOLD_3_M 0x3fU
344 #define SGE_CONM_CTRL_A 0x1094
347 #define EGRTHRESHOLD_M 0x3fU
352 #define EGRTHRESHOLDPACKING_M 0x3fU
358 #define T6_EGRTHRESHOLDPACKING_M 0xffU
362 #define SGE_TIMESTAMP_LO_A 0x1098
363 #define SGE_TIMESTAMP_HI_A 0x109c
366 #define TSOP_M 0x3U
370 #define TSVAL_S 0
371 #define TSVAL_M 0xfffffffU
375 #define SGE_DBFIFO_STATUS_A 0x10a4
376 #define SGE_DBVFIFO_SIZE_A 0x113c
379 #define HP_INT_THRESH_M 0xfU
383 #define LP_INT_THRESH_M 0xfU
386 #define SGE_DOORBELL_CONTROL_A 0x10a8
396 #define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
399 #define TIMERVALUE0_M 0xffffU
403 #define TIMERVALUE1_S 0
404 #define TIMERVALUE1_M 0xffffU
408 #define SGE_TIMER_VALUE_2_AND_3_A 0x10bc
411 #define TIMERVALUE2_M 0xffffU
415 #define TIMERVALUE3_S 0
416 #define TIMERVALUE3_M 0xffffU
420 #define SGE_TIMER_VALUE_4_AND_5_A 0x10c0
423 #define TIMERVALUE4_M 0xffffU
427 #define TIMERVALUE5_S 0
428 #define TIMERVALUE5_M 0xffffU
432 #define SGE_DEBUG_INDEX_A 0x10cc
433 #define SGE_DEBUG_DATA_HIGH_A 0x10d0
434 #define SGE_DEBUG_DATA_LOW_A 0x10d4
436 #define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8
437 #define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc
438 #define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8
440 #define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
441 #define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
443 #define SGE_ERROR_STATS_A 0x1100
453 #define ERROR_QID_S 0
454 #define ERROR_QID_M 0x1ffffU
458 #define HP_INT_THRESH_M 0xfU
462 #define HP_COUNT_M 0x7ffU
466 #define LP_INT_THRESH_M 0xfU
469 #define LP_COUNT_S 0
470 #define LP_COUNT_M 0x7ffU
474 #define LP_INT_THRESH_T5_M 0xfffU
477 #define LP_COUNT_T5_S 0
478 #define LP_COUNT_T5_M 0x3ffffU
481 #define SGE_DOORBELL_CONTROL_A 0x10a8
483 #define SGE_STAT_TOTAL_A 0x10e4
484 #define SGE_STAT_MATCH_A 0x10e8
485 #define SGE_STAT_CFG_A 0x10ec
491 #define STATSOURCE_T5_M 0xfU
495 #define T6_STATMODE_S 0
498 #define SGE_DBFIFO_STATUS2_A 0x1118
501 #define HP_INT_THRESH_T5_M 0xfU
504 #define HP_COUNT_T5_S 0
505 #define HP_COUNT_T5_M 0x3ffU
512 #define DROPPED_DB_S 0
516 #define SGE_CTXT_CMD_A 0x11fc
517 #define SGE_DBQ_CTXT_BADDR_A 0x1084
520 #define PCIE_PF_CFG_A 0x40
523 #define AIVEC_M 0x3ffU
526 #define PCIE_PF_CLI_A 0x44
527 #define PCIE_INT_CAUSE_A 0x3004
645 #define MSIADDRLPERR_S 0
713 #define MSTGRPPERR_S 0
717 #define PCIE_NONFAT_ERR_A 0x3010
718 #define PCIE_CFG_SPACE_REQ_A 0x3060
719 #define PCIE_CFG_SPACE_DATA_A 0x3064
720 #define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
723 #define PCIEOFST_M 0x3fffffU
727 #define BIR_M 0x3U
731 #define WINDOW_S 0
732 #define WINDOW_M 0xffU
736 #define PCIE_MEM_ACCESS_OFFSET_A 0x306c
749 #define REGISTER_S 0
756 #define PFNUM_S 0
759 #define PCIE_FW_A 0x30b8
760 #define PCIE_FW_PF_A 0x30bc
762 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908
788 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
843 #define MC_INT_CAUSE_A 0x7518
844 #define MC_P_INT_CAUSE_A 0x41318
854 #define PERR_INT_CAUSE_S 0
858 #define MC_ECC_STATUS_A 0x751c
859 #define MC_P_ECC_STATUS_A 0x4131c
862 #define ECC_CECNT_M 0xffffU
866 #define ECC_UECNT_S 0
867 #define ECC_UECNT_M 0xffffU
871 #define MC_BIST_CMD_A 0x7600
880 #define BIST_OPCODE_S 0
883 #define MC_BIST_CMD_ADDR_A 0x7604
884 #define MC_BIST_CMD_LEN_A 0x7608
885 #define MC_BIST_DATA_PATTERN_A 0x760c
887 #define MC_BIST_STATUS_RDATA_A 0x7688
890 #define MA_EDRAM0_BAR_A 0x77c0
893 #define EDRAM0_BASE_M 0xfffU
896 #define EDRAM0_SIZE_S 0
897 #define EDRAM0_SIZE_M 0xfffU
901 #define MA_EDRAM1_BAR_A 0x77c4
904 #define EDRAM1_BASE_M 0xfffU
907 #define EDRAM1_SIZE_S 0
908 #define EDRAM1_SIZE_M 0xfffU
912 #define MA_EXT_MEMORY_BAR_A 0x77c8
915 #define EXT_MEM_BASE_M 0xfffU
919 #define EXT_MEM_SIZE_S 0
920 #define EXT_MEM_SIZE_M 0xfffU
924 #define MA_EXT_MEMORY1_BAR_A 0x7808
927 #define EXT_MEM1_BASE_M 0xfffU
930 #define EXT_MEM1_SIZE_S 0
931 #define EXT_MEM1_SIZE_M 0xfffU
935 #define MA_EXT_MEMORY0_BAR_A 0x77c8
938 #define EXT_MEM0_BASE_M 0xfffU
941 #define EXT_MEM0_SIZE_S 0
942 #define EXT_MEM0_SIZE_M 0xfffU
946 #define MA_TARGET_MEM_ENABLE_A 0x77d8
956 #define EDRAM0_ENABLE_S 0
968 #define MA_INT_CAUSE_A 0x77e0
974 #define MEM_WRAP_INT_CAUSE_S 0
978 #define MA_INT_WRAP_STATUS_A 0x77e4
981 #define MEM_WRAP_ADDRESS_M 0xfffffffU
984 #define MEM_WRAP_CLIENT_NUM_S 0
985 #define MEM_WRAP_CLIENT_NUM_M 0xfU
989 #define MA_PARITY_ERROR_STATUS_A 0x77f4
990 #define MA_PARITY_ERROR_STATUS1_A 0x77f4
991 #define MA_PARITY_ERROR_STATUS2_A 0x7804
994 #define EDC_0_BASE_ADDR 0x7900
996 #define EDC_BIST_CMD_A 0x7904
997 #define EDC_BIST_CMD_ADDR_A 0x7908
998 #define EDC_BIST_CMD_LEN_A 0x790c
999 #define EDC_BIST_DATA_PATTERN_A 0x7910
1000 #define EDC_BIST_STATUS_RDATA_A 0x7928
1001 #define EDC_INT_CAUSE_A 0x7978
1015 #define EDC_ECC_STATUS_A 0x797c
1018 #define EDC_1_BASE_ADDR 0x7980
1021 #define CIM_BOOT_CFG_A 0x7b00
1022 #define CIM_SDRAM_BASE_ADDR_A 0x7b14
1023 #define CIM_SDRAM_ADDR_SIZE_A 0x7b18
1024 #define CIM_EXTMEM2_BASE_ADDR_A 0x7b1c
1025 #define CIM_EXTMEM2_ADDR_SIZE_A 0x7b20
1026 #define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290
1028 #define BOOTADDR_M 0xffffff00U
1030 #define UPCRST_S 0
1034 #define CIM_PF_MAILBOX_DATA_A 0x240
1035 #define CIM_PF_MAILBOX_CTRL_A 0x280
1045 #define MBOWNER_S 0
1046 #define MBOWNER_M 0x3U
1050 #define CIM_PF_HOST_INT_ENABLE_A 0x288
1056 #define CIM_PF_HOST_INT_CAUSE_A 0x28c
1062 #define CIM_HOST_INT_CAUSE_A 0x7b2c
1076 #define UPACCNONZERO_S 0
1136 #define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34
1258 #define RSVDSPACEINT_S 0
1268 #define DBGLAWPTR_M 0x7fU
1275 #define DBGLARPTR_S 0
1276 #define DBGLARPTR_M 0x7fU
1279 #define TP_DBG_LA_DATAL_A 0x7ed8
1280 #define TP_DBG_LA_CONFIG_A 0x7ed4
1281 #define TP_OUT_CONFIG_A 0x7d04
1282 #define TP_GLOBAL_CONFIG_A 0x7d08
1284 #define TP_CMM_TCB_BASE_A 0x7d10
1285 #define TP_CMM_MM_BASE_A 0x7d14
1286 #define TP_CMM_TIMER_BASE_A 0x7d18
1287 #define TP_PMM_TX_BASE_A 0x7d20
1288 #define TP_PMM_RX_BASE_A 0x7d28
1289 #define TP_PMM_RX_PAGE_SIZE_A 0x7d2c
1290 #define TP_PMM_RX_MAX_PAGE_A 0x7d30
1291 #define TP_PMM_TX_PAGE_SIZE_A 0x7d34
1292 #define TP_PMM_TX_MAX_PAGE_A 0x7d38
1293 #define TP_CMM_MM_MAX_PSTRUCT_A 0x7e6c
1300 #define PMTXNUMCHN_M 0x3U
1303 #define PMTXMAXPAGE_S 0
1304 #define PMTXMAXPAGE_M 0x1fffffU
1307 #define PMRXMAXPAGE_S 0
1308 #define PMRXMAXPAGE_M 0x1fffffU
1312 #define DBGLAMODE_M 0x3U
1316 #define FIVETUPLELOOKUP_M 0x3U
1320 #define TP_PARA_REG2_A 0x7d68
1323 #define MAXRXDATA_M 0xffffU
1326 #define TP_TIMER_RESOLUTION_A 0x7d90
1329 #define TIMERRESOLUTION_M 0xffU
1333 #define TIMESTAMPRESOLUTION_M 0xffU
1337 #define DELAYEDACKRESOLUTION_S 0
1338 #define DELAYEDACKRESOLUTION_M 0xffU
1342 #define TP_SHIFT_CNT_A 0x7dc0
1343 #define TP_RXT_MIN_A 0x7d98
1344 #define TP_RXT_MAX_A 0x7d9c
1345 #define TP_PERS_MIN_A 0x7da0
1346 #define TP_PERS_MAX_A 0x7da4
1347 #define TP_KEEP_IDLE_A 0x7da8
1348 #define TP_KEEP_INTVL_A 0x7dac
1349 #define TP_INIT_SRTT_A 0x7db0
1350 #define TP_DACK_TIMER_A 0x7db4
1351 #define TP_FINWAIT2_TIMER_A 0x7db8
1353 #define INITSRTT_S 0
1354 #define INITSRTT_M 0xffffU
1357 #define PERSMAX_S 0
1358 #define PERSMAX_M 0x3fffffffU
1363 #define SYNSHIFTMAX_M 0xffU
1368 #define RXTSHIFTMAXR1_M 0xfU
1373 #define RXTSHIFTMAXR2_M 0xfU
1378 #define PERSHIFTBACKOFFMAX_M 0xfU
1384 #define PERSHIFTMAX_M 0xfU
1389 #define KEEPALIVEMAXR1_M 0xfU
1393 #define KEEPALIVEMAXR2_S 0
1394 #define KEEPALIVEMAXR2_M 0xfU
1401 #define TP_CCTRL_TABLE_A 0x7ddc
1402 #define TP_MTU_TABLE_A 0x7de4
1408 #define MTUWIDTH_M 0xfU
1412 #define MTUVALUE_S 0
1413 #define MTUVALUE_M 0x3fffU
1417 #define TP_RSS_LKP_TABLE_A 0x7dec
1418 #define TP_CMM_MM_RX_FLST_BASE_A 0x7e60
1419 #define TP_CMM_MM_TX_FLST_BASE_A 0x7e64
1420 #define TP_CMM_MM_PS_FLST_BASE_A 0x7e68
1427 #define LKPTBLQUEUE1_M 0x3ffU
1430 #define LKPTBLQUEUE0_S 0
1431 #define LKPTBLQUEUE0_M 0x3ffU
1434 #define TP_PIO_ADDR_A 0x7e40
1435 #define TP_PIO_DATA_A 0x7e44
1436 #define TP_MIB_INDEX_A 0x7e50
1437 #define TP_MIB_DATA_A 0x7e54
1438 #define TP_INT_CAUSE_A 0x7e74
1444 #define TP_TX_ORATE_A 0x7ebc
1447 #define OFDRATE3_M 0xffU
1451 #define OFDRATE2_M 0xffU
1455 #define OFDRATE1_M 0xffU
1458 #define OFDRATE0_S 0
1459 #define OFDRATE0_M 0xffU
1462 #define TP_TX_TRATE_A 0x7ed0
1465 #define TNLRATE3_M 0xffU
1469 #define TNLRATE2_M 0xffU
1473 #define TNLRATE1_M 0xffU
1476 #define TNLRATE0_S 0
1477 #define TNLRATE0_M 0xffU
1480 #define TP_VLAN_PRI_MAP_A 0x140
1518 #define FCOE_S 0
1530 #define TP_INGRESS_CONFIG_A 0x141
1540 #define TP_MIB_MAC_IN_ERR_0_A 0x0
1541 #define TP_MIB_HDR_IN_ERR_0_A 0x4
1542 #define TP_MIB_TCP_IN_ERR_0_A 0x8
1543 #define TP_MIB_TCP_OUT_RST_A 0xc
1544 #define TP_MIB_TCP_IN_SEG_HI_A 0x10
1545 #define TP_MIB_TCP_IN_SEG_LO_A 0x11
1546 #define TP_MIB_TCP_OUT_SEG_HI_A 0x12
1547 #define TP_MIB_TCP_OUT_SEG_LO_A 0x13
1548 #define TP_MIB_TCP_RXT_SEG_HI_A 0x14
1549 #define TP_MIB_TCP_RXT_SEG_LO_A 0x15
1550 #define TP_MIB_TNL_CNG_DROP_0_A 0x18
1551 #define TP_MIB_OFD_CHN_DROP_0_A 0x1c
1552 #define TP_MIB_TCP_V6IN_ERR_0_A 0x28
1553 #define TP_MIB_TCP_V6OUT_RST_A 0x2c
1554 #define TP_MIB_OFD_ARP_DROP_A 0x36
1555 #define TP_MIB_CPL_IN_REQ_0_A 0x38
1556 #define TP_MIB_CPL_OUT_RSP_0_A 0x3c
1557 #define TP_MIB_TNL_DROP_0_A 0x44
1558 #define TP_MIB_FCOE_DDP_0_A 0x48
1559 #define TP_MIB_FCOE_DROP_0_A 0x4c
1560 #define TP_MIB_FCOE_BYTE_0_HI_A 0x50
1561 #define TP_MIB_OFD_VLN_DROP_0_A 0x58
1562 #define TP_MIB_USM_PKTS_A 0x5c
1563 #define TP_MIB_RQE_DFR_PKT_A 0x64
1565 #define ULP_TX_INT_CAUSE_A 0x8dcc
1566 #define ULP_TX_TPT_LLIMIT_A 0x8dd4
1567 #define ULP_TX_TPT_ULIMIT_A 0x8dd8
1568 #define ULP_TX_PBL_LLIMIT_A 0x8ddc
1569 #define ULP_TX_PBL_ULIMIT_A 0x8de0
1570 #define ULP_TX_ERR_TABLE_BASE_A 0x8e04
1588 #define PM_RX_INT_CAUSE_A 0x8fdc
1589 #define PM_RX_STAT_CONFIG_A 0x8fc8
1590 #define PM_RX_STAT_COUNT_A 0x8fcc
1591 #define PM_RX_STAT_LSB_A 0x8fd0
1592 #define PM_RX_DBG_CTRL_A 0x8fd0
1593 #define PM_RX_DBG_DATA_A 0x8fd4
1594 #define PM_RX_DBG_STAT_MSB_A 0x10013
1596 #define PMRX_FRAMING_ERROR_F 0x003ffff0U
1614 #define PMRX_E_PCMD_PAR_ERROR_S 0
1618 #define PM_TX_INT_CAUSE_A 0x8ffc
1619 #define PM_TX_STAT_CONFIG_A 0x8fe8
1620 #define PM_TX_STAT_COUNT_A 0x8fec
1621 #define PM_TX_STAT_LSB_A 0x8ff0
1622 #define PM_TX_DBG_CTRL_A 0x8ff0
1623 #define PM_TX_DBG_DATA_A 0x8ff4
1624 #define PM_TX_DBG_STAT_MSB_A 0x1001a
1642 #define PMTX_FRAMING_ERROR_F 0x0ffffff0U
1652 #define PMTX_C_PCMD_PAR_ERROR_S 0
1656 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
1657 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
1658 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
1659 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
1660 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
1661 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
1662 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
1663 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
1664 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
1665 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
1666 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
1667 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
1668 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430
1669 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434
1670 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
1671 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
1672 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
1673 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
1674 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
1675 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
1676 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
1677 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
1678 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
1679 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
1680 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
1681 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
1682 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
1683 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
1684 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
1685 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
1686 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
1687 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
1688 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
1689 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
1690 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
1691 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
1692 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
1693 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
1694 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
1695 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
1696 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
1697 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
1698 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
1699 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
1700 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
1701 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
1702 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
1703 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
1704 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
1705 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
1706 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
1707 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
1708 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
1709 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
1710 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
1711 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
1712 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
1713 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
1714 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
1715 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
1716 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
1717 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
1718 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
1719 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
1720 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
1721 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
1722 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
1723 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
1724 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
1725 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
1726 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
1727 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
1728 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
1729 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
1730 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
1731 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
1732 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
1733 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
1734 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
1735 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
1736 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
1737 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
1738 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
1739 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
1740 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
1741 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
1742 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
1743 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
1744 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
1745 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
1746 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
1747 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
1748 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
1749 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
1750 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590
1751 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594
1752 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
1753 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
1754 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
1755 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
1756 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
1757 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
1758 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
1759 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
1760 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
1761 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
1762 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
1763 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
1764 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
1765 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
1766 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
1767 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
1768 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
1769 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
1770 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
1771 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
1772 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
1773 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
1774 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
1775 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
1776 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
1777 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
1778 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
1779 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
1780 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
1781 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
1782 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
1783 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
1784 #define MAC_PORT_MAGIC_MACID_LO 0x824
1785 #define MAC_PORT_MAGIC_MACID_HI 0x828
1787 #define MAC_PORT_EPIO_DATA0_A 0x8c0
1788 #define MAC_PORT_EPIO_DATA1_A 0x8c4
1789 #define MAC_PORT_EPIO_DATA2_A 0x8c8
1790 #define MAC_PORT_EPIO_DATA3_A 0x8cc
1791 #define MAC_PORT_EPIO_OP_A 0x8d0
1793 #define MAC_PORT_CFG2_A 0x818
1795 #define MPS_CMN_CTL_A 0x9000
1797 #define NUMPORTS_S 0
1798 #define NUMPORTS_M 0x3U
1801 #define MPS_INT_CAUSE_A 0x9008
1802 #define MPS_TX_INT_CAUSE_A 0x9408
1817 #define TXDESCFIFO_M 0xfU
1821 #define TXDATAFIFO_M 0xfU
1828 #define TPFIFO_S 0
1829 #define TPFIFO_M 0xfU
1832 #define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614
1833 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620
1834 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c
1836 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
1837 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
1838 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
1839 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
1840 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
1841 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
1842 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
1843 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
1844 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
1845 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
1846 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
1847 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
1848 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
1849 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
1850 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
1851 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
1852 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
1853 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
1854 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
1855 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
1856 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
1857 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
1858 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
1859 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
1860 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
1861 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
1862 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
1863 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
1864 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
1865 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
1866 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
1867 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
1869 #define MPS_TRC_CFG_A 0x9800
1887 #define TRCMULTIFILTER_S 0
1891 #define MPS_TRC_RSS_CONTROL_A 0x9808
1892 #define MPS_TRC_FILTER1_RSS_CONTROL_A 0x9ff4
1893 #define MPS_TRC_FILTER2_RSS_CONTROL_A 0x9ffc
1894 #define MPS_TRC_FILTER3_RSS_CONTROL_A 0xa004
1895 #define MPS_T5_TRC_RSS_CONTROL_A 0xa00c
1900 #define QUEUENUMBER_S 0
1912 #define TFPORT_M 0xfU
1917 #define TFLENGTH_M 0x1fU
1921 #define TFOFFSET_S 0
1922 #define TFOFFSET_M 0x1fU
1935 #define T5_TFPORT_M 0x1fU
1939 #define MPS_TRC_FILTER_MATCH_CTL_A_A 0x9810
1940 #define MPS_TRC_FILTER_MATCH_CTL_B_A 0x9820
1943 #define TFMINPKTSIZE_M 0x1ffU
1947 #define TFCAPTUREMAX_S 0
1948 #define TFCAPTUREMAX_M 0x3fffU
1952 #define MPS_TRC_FILTER0_MATCH_A 0x9c00
1953 #define MPS_TRC_FILTER0_DONT_CARE_A 0x9c80
1954 #define MPS_TRC_FILTER1_MATCH_A 0x9d00
1956 #define TP_RSS_CONFIG_A 0x7df0
2066 #define DISABLE_S 0
2070 #define TP_RSS_CONFIG_TNL_A 0x7df4
2073 #define MASKSIZE_M 0xfU
2078 #define MASKFILTER_M 0x7ffU
2082 #define USEWIRECH_S 0
2094 #define TP_RSS_CONFIG_OFD_A 0x7df8
2101 #define RRCPLQUEWIDTH_M 0xfU
2105 #define TP_RSS_CONFIG_SYN_A 0x7dfc
2106 #define TP_RSS_CONFIG_VRT_A 0x7e00
2133 #define HASHDELAY_M 0xfU
2138 #define VFWRADDR_M 0x7fU
2143 #define KEYMODE_M 0x3U
2155 #define KEYWRADDR_S 0
2156 #define KEYWRADDR_M 0xfU
2161 #define KEYWRADDRX_M 0x3U
2170 #define LKPIDXSIZE_M 0x3U
2174 #define TP_RSS_VFL_CONFIG_A 0x3a
2175 #define TP_RSS_VFH_CONFIG_A 0x3b
2198 #define DEFAULTQUEUE_M 0x3ffU
2213 #define KEYINDEX_S 0
2214 #define KEYINDEX_M 0xfU
2250 #define IVFWIDTH_M 0xfU
2255 #define CH1DEFAULTQUEUE_M 0x3ffU
2259 #define CH0DEFAULTQUEUE_S 0
2260 #define CH0DEFAULTQUEUE_M 0x3ffU
2265 #define VFLKPIDX_M 0xffU
2269 #define T6_VFWRADDR_M 0xffU
2273 #define TP_RSS_CONFIG_CNG_A 0x7e04
2274 #define TP_RSS_SECRET_KEY0_A 0x40
2275 #define TP_RSS_PF0_CONFIG_A 0x30
2276 #define TP_RSS_PF_MAP_A 0x38
2277 #define TP_RSS_PF_MSK_A 0x39
2281 #define PF0LKPIDX_M 0x7U
2284 #define PF1MSKSIZE_M 0xfU
2358 #define QUEUE_S 0
2359 #define QUEUE_M 0x3ffU
2363 #define MPS_TRC_INT_CAUSE_A 0x985c
2370 #define PKTFIFO_M 0xfU
2373 #define FILTMEM_S 0
2374 #define FILTMEM_M 0xfU
2377 #define MPS_CLS_INT_CAUSE_A 0xd028
2387 #define MATCHSRAM_S 0
2391 #define MPS_RX_PG_RSV0_A 0x11010
2392 #define MPS_RX_PG_RSV4_A 0x11020
2393 #define MPS_RX_PERR_INT_CAUSE_A 0x11074
2394 #define MPS_RX_MAC_BG_PG_CNT0_A 0x11208
2395 #define MPS_RX_LPBK_BG_PG_CNT0_A 0x11218
2397 #define MPS_CLS_TCAM_Y_L_A 0xf000
2398 #define MPS_CLS_TCAM_DATA0_A 0xf000
2399 #define MPS_CLS_TCAM_DATA1_A 0xf004
2402 #define VIDL_M 0xffffU
2406 #define DATALKPTYPE_M 0x3U
2410 #define DATAPORTNUM_M 0xfU
2421 #define DATAVIDH1_S 0
2422 #define DATAVIDH1_M 0x7fU
2426 #define USED_M 0x7ffU
2429 #define ALLOC_S 0
2430 #define ALLOC_M 0x7ffU
2434 #define T5_USED_M 0xfffU
2437 #define T5_ALLOC_S 0
2438 #define T5_ALLOC_M 0xfffU
2441 #define DMACH_S 0
2442 #define DMACH_M 0xffffU
2445 #define MPS_CLS_TCAM_X_L_A 0xf008
2446 #define MPS_CLS_TCAM_DATA2_CTL_A 0xf008
2467 #define MPS_CLS_SRAM_L_A 0xe000
2472 #define T6_SRAM_PRIO3_M 0x7U
2476 #define T6_SRAM_PRIO2_M 0x7U
2480 #define T6_SRAM_PRIO1_M 0x7U
2484 #define T6_SRAM_PRIO0_M 0x7U
2496 #define T6_PF_M 0x7U
2503 #define T6_VF_S 0
2504 #define T6_VF_M 0xffU
2507 #define MPS_CLS_SRAM_H_A 0xe004
2522 #define PF_M 0x7U
2529 #define VF_S 0
2530 #define VF_M 0x7fU
2534 #define SRAM_PRIO3_M 0x7U
2538 #define SRAM_PRIO2_M 0x7U
2542 #define SRAM_PRIO1_M 0x7U
2546 #define SRAM_PRIO0_M 0x7U
2553 #define PORTMAP_S 0
2554 #define PORTMAP_M 0xfU
2557 #define CPL_INTR_CAUSE_A 0x19054
2579 #define ZERO_SWITCH_ERROR_S 0
2583 #define SMB_INT_CAUSE_A 0x19090
2597 #define ULP_RX_INT_CAUSE_A 0x19158
2598 #define ULP_RX_ISCSI_LLIMIT_A 0x1915c
2599 #define ULP_RX_ISCSI_ULIMIT_A 0x19160
2600 #define ULP_RX_ISCSI_TAGMASK_A 0x19164
2601 #define ULP_RX_ISCSI_PSZ_A 0x19168
2602 #define ULP_RX_TDDP_LLIMIT_A 0x1916c
2603 #define ULP_RX_TDDP_ULIMIT_A 0x19170
2604 #define ULP_RX_STAG_LLIMIT_A 0x1917c
2605 #define ULP_RX_STAG_ULIMIT_A 0x19180
2606 #define ULP_RX_RQ_LLIMIT_A 0x19184
2607 #define ULP_RX_RQ_ULIMIT_A 0x19188
2608 #define ULP_RX_PBL_LLIMIT_A 0x1918c
2609 #define ULP_RX_PBL_ULIMIT_A 0x19190
2610 #define ULP_RX_CTX_BASE_A 0x19194
2611 #define ULP_RX_RQUDP_LLIMIT_A 0x191a4
2612 #define ULP_RX_RQUDP_ULIMIT_A 0x191a8
2613 #define ULP_RX_LA_CTL_A 0x1923c
2614 #define ULP_RX_LA_RDPTR_A 0x19240
2615 #define ULP_RX_LA_RDDATA_A 0x19244
2616 #define ULP_RX_LA_WRPTR_A 0x19248
2627 #define HPZ0_S 0
2630 #define ULP_RX_TDDP_PSZ_A 0x19178
2633 #define SF_DATA_A 0x193f8
2634 #define SF_OP_A 0x193fc
2651 #define OP_S 0
2655 #define PL_PF_INT_CAUSE_A 0x3c0
2665 #define PL_PF_INT_ENABLE_A 0x3c4
2666 #define PL_PF_CTL_A 0x3c8
2668 #define PL_WHOAMI_A 0x19400
2671 #define SOURCEPF_M 0x7U
2675 #define T6_SOURCEPF_M 0x7U
2678 #define PL_INT_CAUSE_A 0x1940c
2768 #define CIM_S 0
2776 #define PL_INT_ENABLE_A 0x19410
2777 #define PL_INT_MAP0_A 0x19414
2778 #define PL_RST_A 0x19428
2784 #define PIORSTMODE_S 0
2788 #define PL_PL_INT_CAUSE_A 0x19430
2794 #define PERRVFID_S 0
2798 #define PL_REV_A 0x1943c
2800 #define REV_S 0
2801 #define REV_M 0xfU
2817 #define LE_DB_CONFIG_A 0x19c04
2818 #define LE_DB_SERVER_INDEX_A 0x19c18
2819 #define LE_DB_SRVR_START_INDEX_A 0x19c18
2820 #define LE_DB_ACT_CNT_IPV4_A 0x19c20
2821 #define LE_DB_ACT_CNT_IPV6_A 0x19c24
2822 #define LE_DB_HASH_TID_BASE_A 0x19c30
2823 #define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c30
2824 #define LE_DB_INT_CAUSE_A 0x19c3c
2825 #define LE_DB_TID_HASHBASE_A 0x19df8
2826 #define T6_LE_DB_HASH_TID_BASE_A 0x19df8
2857 #define BASEADDR_M 0x1fffffffU
2868 #define NCSI_INT_CAUSE_A 0x1a0d8
2882 #define RXFIFO_PRTY_ERR_S 0
2886 #define XGMAC_PORT_CFG2_A 0x1018
2896 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024
2897 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028
2899 #define XGMAC_PORT_EPIO_DATA0_A 0x10c0
2900 #define XGMAC_PORT_EPIO_DATA1_A 0x10c4
2901 #define XGMAC_PORT_EPIO_DATA2_A 0x10c8
2902 #define XGMAC_PORT_EPIO_DATA3_A 0x10cc
2903 #define XGMAC_PORT_EPIO_OP_A 0x10d0
2909 #define ADDRESS_S 0
2912 #define MAC_PORT_INT_CAUSE_A 0x8dc
2913 #define XGMAC_PORT_INT_CAUSE_A 0x10dc
2915 #define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
2917 #define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30
2918 #define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34
2920 #define TX_MOD_QUEUE_REQ_MAP_S 0
2932 #define TX_MODQ_WEIGHT0_S 0
2935 #define TP_TX_SCHED_HDR_A 0x23
2936 #define TP_TX_SCHED_FIFO_A 0x24
2937 #define TP_TX_SCHED_PCMD_A 0x25
2942 #define T5_PORT0_BASE 0x30000
2943 #define T5_PORT_STRIDE 0x4000
2947 #define MC_0_BASE_ADDR 0x40000
2948 #define MC_1_BASE_ADDR 0x48000
2952 #define MC_P_BIST_CMD_A 0x41400
2953 #define MC_P_BIST_CMD_ADDR_A 0x41404
2954 #define MC_P_BIST_CMD_LEN_A 0x41408
2955 #define MC_P_BIST_DATA_PATTERN_A 0x4140c
2956 #define MC_P_BIST_STATUS_RDATA_A 0x41488
2958 #define EDC_T50_BASE_ADDR 0x50000
2960 #define EDC_H_BIST_CMD_A 0x50004
2961 #define EDC_H_BIST_CMD_ADDR_A 0x50008
2962 #define EDC_H_BIST_CMD_LEN_A 0x5000c
2963 #define EDC_H_BIST_DATA_PATTERN_A 0x50010
2964 #define EDC_H_BIST_STATUS_RDATA_A 0x50028
2966 #define EDC_H_ECC_ERR_ADDR_A 0x50084
2967 #define EDC_T51_BASE_ADDR 0x50800
2972 #define PL_VF_REV_A 0x4
2973 #define PL_VF_WHOAMI_A 0x0
2974 #define PL_VF_REVISION_A 0x8
2977 #define CIM_HOST_ACC_CTRL_A 0x7b50
2978 #define CIM_HOST_ACC_DATA_A 0x7b54
2979 #define UP_UP_DBG_LA_CFG_A 0x140
2980 #define UP_UP_DBG_LA_DATA_A 0x144
2990 #define CIM_IBQ_DBG_CFG_A 0x7b60
2993 #define IBQDBGADDR_M 0xfffU
3001 #define IBQDBGEN_S 0
3005 #define CIM_OBQ_DBG_CFG_A 0x7b64
3008 #define OBQDBGADDR_M 0xfffU
3016 #define OBQDBGEN_S 0
3020 #define CIM_IBQ_DBG_DATA_A 0x7b68
3021 #define CIM_OBQ_DBG_DATA_A 0x7b6c
3022 #define CIM_DEBUGCFG_A 0x7b70
3023 #define CIM_DEBUGSTS_A 0x7b74
3026 #define POLADBGRDPTR_M 0x1ffU
3030 #define POLADBGWRPTR_M 0x1ffU
3034 #define PILADBGRDPTR_M 0x1ffU
3037 #define PILADBGWRPTR_S 0
3038 #define PILADBGWRPTR_M 0x1ffU
3045 #define CIM_PO_LA_DEBUGDATA_A 0x7b78
3046 #define CIM_PI_LA_DEBUGDATA_A 0x7b7c
3047 #define CIM_PO_LA_MADEBUGDATA_A 0x7b80
3048 #define CIM_PI_LA_MADEBUGDATA_A 0x7b84
3054 #define UPDBGLAEN_S 0
3059 #define UPDBGLARDPTR_M 0xfffU
3063 #define UPDBGLAWRPTR_M 0xfffU
3070 #define CIM_QUEUE_CONFIG_REF_A 0x7b48
3071 #define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
3074 #define CIMQSIZE_M 0x3fU
3078 #define CIMQBASE_M 0x3fU
3081 #define QUEFULLTHRSH_S 0
3082 #define QUEFULLTHRSH_M 0x1ffU
3085 #define UP_IBQ_0_RDADDR_A 0x10
3086 #define UP_IBQ_0_SHADOW_RDADDR_A 0x280
3087 #define UP_OBQ_0_REALADDR_A 0x104
3088 #define UP_OBQ_0_SHADOW_REALADDR_A 0x394
3090 #define IBQRDADDR_S 0
3091 #define IBQRDADDR_M 0x1fffU
3094 #define IBQWRADDR_S 0
3095 #define IBQWRADDR_M 0x1fffU
3098 #define QUERDADDR_S 0
3099 #define QUERDADDR_M 0x7fffU
3102 #define QUEREMFLITS_S 0
3103 #define QUEREMFLITS_M 0x7ffU
3107 #define QUEEOPCNT_M 0xfffU
3110 #define QUESOPCNT_S 0
3111 #define QUESOPCNT_M 0xfffU
3122 #define QUENUMSELECT_S 0