Lines Matching +full:multi +full:- +full:instance

14  *      - Redistributions of source code must retain the above
18  *      - Redistributions in binary form must reproduce the above
41    are looking for barriers to use with cache-coherent multi-threaded
47      - CPU attached address space (the CPU memory could be a range of things:
48        cached/uncached/non-temporal CPU DRAM, uncached MMIO space in another
53      - A DMA initiator on a bus. For instance a PCI-E device issuing
57    happens if a MemRd TLP is sent in via PCI-E relative to a CPU WRITE to the
80    memory types or non-temporal stores are required to use SFENCE in their own
117    from the device - eg by reading a MMIO register or seeing that CPU memory is
123    For instance, this would be used after testing a valid bit in a memory
167       wqe->addr = ...;
168       wqe->flags = ...;
170       wqe->valid = 1;
195    PCI-E MemWr TLPs from the CPU.
223 /* Prevent WC writes from being re-ordered relative to other MMIO
226    This must act as a barrier to prevent write re-ordering from different
236    PCI-E MemWr TLPs from the CPU.
254    Any access to a multi-value WC region must ensure that multiple cpus do not
279 	 * to force-flush the WC buffers quickly, and this SFENCE can be  in mmio_wc_spinunlock()