Lines Matching +full:power +full:- +full:stable +full:- +full:time
1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
7 <!-- Changed by: stenn, 03-Jan-2020 -->
13 <!-- #BeginDate format:En2m -->3-Jan-2020 02:12<!-- #EndDate -->
18 <li class="inline"><a href="#pll">Phase-Lock Loop Operations</a></li>
24 …-lock feedback loop. It is an intricately crafted algorithm that automatically adapts for optimum…
29 …The loop filter implements a type-2 proportional-integrator controller (PIC). The PIC can minimiz…
30 …time in order to avoid setting the clock backward. In FLL mode the phase predictor is not used, w…
31 …time constant</em>, which results in a "stiffness" depending on the jitter of the availa…
33 …stable and satisfies the Nyquist criterion, which requires that the sampling rate be at least twic…
34 …re affected by the time constant and poll interval. At the default poll interval of 64 s and a st…
36 …time. The response scales exactly with step amplitude, so that the response to a 10-ms step has t…
37 …time constant, and thus the poll interval, depends on the network time jitter and the oscillator f…
38 …xtreme cases not likely to be encountered in normal operation, the system time can be stepped forw…
41 …e devices when the power is turned off, the battery backup clock offset error can increase as much…
43 …gence time. In a cold start when no frequency file is available, the reference implementation fir…
44 …time constant. This is designed to quickly reduce the clock offset error without causing a freque…
45 <p>Another concern at restart is the time necessary for the select and cluster algorithms to refine…