43 bool X86Disassembler::isRegisterOperand(const Record *Rec) {  in isRegisterOperand()  argument
44   return Rec->isSubClassOf("RegisterClass") ||  in isRegisterOperand()
45          Rec->isSubClassOf("RegisterOperand");  in isRegisterOperand()
48 bool X86Disassembler::isMemoryOperand(const Record *Rec) {  in isMemoryOperand()  argument
49   return Rec->isSubClassOf("Operand") &&  in isMemoryOperand()
50          Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";  in isMemoryOperand()
53 bool X86Disassembler::isImmediateOperand(const Record *Rec) {  in isImmediateOperand()  argument
54   return Rec->isSubClassOf("Operand") &&  in isImmediateOperand()
55          Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";  in isImmediateOperand()
112   const Record *Rec = insn.TheDef;  in RecognizableInstrBase()  local
113   assert(Rec->isSubClassOf("X86Inst") && "Not a X86 Instruction");  in RecognizableInstrBase()
114   OpPrefix = byteFromRec(Rec, "OpPrefixBits");  in RecognizableInstrBase()
115   OpMap = byteFromRec(Rec, "OpMapBits");  in RecognizableInstrBase()
116   Opcode = byteFromRec(Rec, "Opcode");  in RecognizableInstrBase()
117   Form = byteFromRec(Rec, "FormBits");  in RecognizableInstrBase()
118   Encoding = byteFromRec(Rec, "OpEncBits");  in RecognizableInstrBase()
119   OpSize = byteFromRec(Rec, "OpSizeBits");  in RecognizableInstrBase()
120   AdSize = byteFromRec(Rec, "AdSizeBits");  in RecognizableInstrBase()
121   HasREX_W = Rec->getValueAsBit("hasREX_W");  in RecognizableInstrBase()
122   HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");  in RecognizableInstrBase()
123   IgnoresW = Rec->getValueAsBit("IgnoresW");  in RecognizableInstrBase()
124   IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");  in RecognizableInstrBase()
125   HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2");  in RecognizableInstrBase()
126   HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");  in RecognizableInstrBase()
127   HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");  in RecognizableInstrBase()
128   HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");  in RecognizableInstrBase()
129   HasEVEX_NF = Rec->getValueAsBit("hasEVEX_NF");  in RecognizableInstrBase()
130   HasTwoConditionalOps = Rec->getValueAsBit("hasTwoConditionalOps");  in RecognizableInstrBase()
131   IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");  in RecognizableInstrBase()
132   IsAsmParserOnly = Rec->getValueAsBit("isAsmParserOnly");  in RecognizableInstrBase()
133   ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");  in RecognizableInstrBase()
134   CD8_Scale = byteFromRec(Rec, "CD8_Scale");  in RecognizableInstrBase()
135   HasVEX_L = Rec->getValueAsBit("hasVEX_L");  in RecognizableInstrBase()
137       byteFromRec(Rec, "explicitOpPrefixBits") == X86Local::ExplicitREX2;  in RecognizableInstrBase()
151     : RecognizableInstrBase(insn), Rec(insn.TheDef), Name(Rec->getName().str()),  in RecognizableInstr()
156   std::vector<Record *> Predicates = Rec->getValueAsListOfDefs("Predicates");  in RecognizableInstr()
430   StringRef typeName = (*Operands)[operandIndex].Rec->getName();  in handleOperand()