Lines Matching +full:ccode +full:- +full:map
1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
31 StringRef(I->FlattenAsmStringVariants(I->AsmString, Variant)) in getMnemonic()
36 // Replace it with "CC" in-place. in getMnemonic()
44 return Rec->isSubClassOf("RegisterClass") || in isRegisterOperand()
45 Rec->isSubClassOf("RegisterOperand"); in isRegisterOperand()
49 return Rec->isSubClassOf("Operand") && in isMemoryOperand()
50 Rec->getValueAsString("OperandType") == "OPERAND_MEMORY"; in isMemoryOperand()
54 return Rec->isSubClassOf("Operand") && in isImmediateOperand()
55 Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE"; in isImmediateOperand()
59 if (RegRec->isSubClassOf("RegisterClass")) in getRegOperandSize()
60 return RegRec->getValueAsInt("Alignment"); in getRegOperandSize()
61 if (RegRec->isSubClassOf("RegisterOperand")) in getRegOperandSize()
62 return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment"); in getRegOperandSize()
68 if (MemRec->isSubClassOf("X86MemOperand")) in getMemOperandSize()
69 return MemRec->getValueAsInt("Size"); in getMemOperandSize()
74 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
77 /// @param init - A reference to the BitsInit to be decoded.
78 /// @return - The field, with the first bit in the BitsInit as the lowest
91 if (cast<BitInit>(init.getBit(index))->getValue()) in byteFromBitsInit()
100 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
103 /// @param rec - The record from which to extract the value.
104 /// @param name - The name of the field in the record.
105 /// @return - The field, as translated by byteFromBitsInit().
107 BitsInit *bits = rec->getValueAsBitsInit(name); in byteFromRec()
113 assert(Rec->isSubClassOf("X86Inst") && "Not a X86 Instruction"); in RecognizableInstrBase()
121 HasREX_W = Rec->getValueAsBit("hasREX_W"); in RecognizableInstrBase()
122 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); in RecognizableInstrBase()
123 IgnoresW = Rec->getValueAsBit("IgnoresW"); in RecognizableInstrBase()
124 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); in RecognizableInstrBase()
125 HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2"); in RecognizableInstrBase()
126 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); in RecognizableInstrBase()
127 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); in RecognizableInstrBase()
128 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); in RecognizableInstrBase()
129 HasEVEX_NF = Rec->getValueAsBit("hasEVEX_NF"); in RecognizableInstrBase()
130 HasTwoConditionalOps = Rec->getValueAsBit("hasTwoConditionalOps"); in RecognizableInstrBase()
131 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); in RecognizableInstrBase()
132 IsAsmParserOnly = Rec->getValueAsBit("isAsmParserOnly"); in RecognizableInstrBase()
133 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); in RecognizableInstrBase()
135 HasVEX_L = Rec->getValueAsBit("hasVEX_L"); in RecognizableInstrBase()
151 : RecognizableInstrBase(insn), Rec(insn.TheDef), Name(Rec->getName().str()), in RecognizableInstr()
154 // Check for 64-bit inst which does not require REX in RecognizableInstr()
156 std::vector<Record *> Predicates = Rec->getValueAsListOfDefs("Predicates"); in RecognizableInstr()
158 if (Predicates[i]->getName().contains("Not64Bit") || in RecognizableInstr()
159 Predicates[i]->getName().contains("In32Bit")) { in RecognizableInstr()
163 if (Predicates[i]->getName().contains("In64Bit")) { in RecognizableInstr()
173 if (!insn.TheDef->isSubClassOf("X86Inst")) in processInstr()
424 Spec->operands[operandIndex].encoding = ENCODING_DUP; in handleOperand()
425 Spec->operands[operandIndex].type = in handleOperand()
430 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); in handleOperand()
435 Spec->operands[operandIndex].encoding = encoding; in handleOperand()
436 Spec->operands[operandIndex].type = in handleOperand()
444 Spec->name = Name; in emitInstructionSpecifier()
446 Spec->insnContext = insnContext(); in emitInstructionSpecifier()
552 // - In AVX512 there may be a mask operand here - in emitInstructionSpecifier()
554 // - In AVX, there is a register operand in the VEX.vvvv field here - in emitInstructionSpecifier()
597 // Operand 1 is a memory operand (possibly SIB-extended) in emitInstructionSpecifier()
599 // - In AVX, there is a register operand in the VEX.vvvv field here - in emitInstructionSpecifier()
625 // - In AVX, there is a register operand in the VEX.vvvv field here - in emitInstructionSpecifier()
678 // Operand 2 is a memory operand (possibly SIB-extended) in emitInstructionSpecifier()
679 // - In AVX, there is a register operand in the VEX.vvvv field here - in emitInstructionSpecifier()
778 // Operand 1 is a memory operand (possibly SIB-extended) in emitInstructionSpecifier()
794 // operand 1 is a 16-bit immediate in emitInstructionSpecifier()
795 // operand 2 is an 8-bit immediate in emitInstructionSpecifier()
802 // operand 1 is a 16-bit immediate in emitInstructionSpecifier()
803 // operand 2 is a 16-bit immediate in emitInstructionSpecifier()
815 #define MAP(from, to) case X86Local::MRM_##from: in emitInstructionSpecifier() macro
817 #undef MAP in emitInstructionSpecifier()
829 #define MAP(from, to) case X86Local::MRM_##from: in emitDecodePath() macro
834 llvm_unreachable("Invalid map!"); in emitDecodePath()
922 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); in emitDecodePath()
932 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X); in emitDecodePath()
935 filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0); in emitDecodePath()
945 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); in emitDecodePath()
948 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); in emitDecodePath()
991 #undef MAP in emitDecodePath()
1000 // For instructions with a REX_W prefix, a declared 32-bit register encoding in typeFromString()
1005 // For OpSize16 instructions, a declared 16-bit register or in typeFromString()
1009 // For OpSize32 instructions, a declared 32-bit register or in typeFromString()
1063 TYPE("ccode", TYPE_IMM) in typeFromString()
1148 // For instructions without an OpSize prefix, a declared 16-bit register or in immediateEncodingFromString()
1160 ENCODING("ccode", ENCODING_CC) in immediateEncodingFromString()
1168 // register IDs in 8-bit immediates nowadays. in immediateEncodingFromString()
1363 // For instructions without an OpSize prefix, a declared 16-bit register or in relocationEncodingFromString()
1415 ENCODING("ccode", ENCODING_CC) in opcodeModifierEncodingFromString()