Lines Matching refs:getName

121      << "extern const MCRegisterClass " << Target.getName()  in runEnums()
129 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
165 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
181 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
227 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
367 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) in finalizeDwarfRegNumsKeys()
375 return A.first->getName() == B.first->getName(); in finalizeDwarfRegNumsKeys()
815 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
901 RegStrings.add(std::string(Reg.getName())); in runMCDesc()
938 const std::string &TargetName = std::string(Target.getName()); in runMCDesc()
975 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", " in runMCDesc()
1012 const std::string &Name = RC.getName(); in runMCDesc()
1046 std::string RCName = Order.empty() ? "nullptr" : RC.getName(); in runMCDesc()
1047 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits"; in runMCDesc()
1054 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1112 const std::string &TargetName = std::string(Target.getName()); in runTargetHeader()
1175 const std::string &Name = RC.getName(); in runTargetHeader()
1199 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1240 OS << Idx.getName(); in runTargetDesc()
1253 << Idx.getName() << "\n"; in runTargetDesc()
1263 OS << ", // " << Idx.getName() << '\n'; in runTargetDesc()
1293 << RC.getName() << '\n'; in runTargetDesc()
1326 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1341 OS << "// " << Idx.getName(); in runTargetDesc()
1360 OS << "static const TargetRegisterClass *const " << RC.getName() in runTargetDesc()
1370 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1373 << "static ArrayRef<MCPhysReg> " << RC.getName() in runTargetDesc()
1384 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1393 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1404 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1405 << "RegClass = {\n " << '&' << Target.getName() in runTargetDesc()
1406 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " in runTargetDesc()
1407 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " in runTargetDesc()
1420 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1424 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1439 const std::string &TargetName = std::string(Target.getName()); in runTargetDesc()
1487 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; in runTargetDesc()
1512 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1515 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1516 << " -> " << SRC->getName() << "\n"; in runTargetDesc()
1518 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1545 OS << " {\t// " << RC.getName() << '\n'; in runTargetDesc()
1556 OS << " " << EnumValue << ",\t// " << RC.getName() << ':' in runTargetDesc()
1557 << Idx.getName(); in runTargetDesc()
1561 OS << " -> " << SubRegClass->getName(); in runTargetDesc()
1619 << ", // " << Reg.getName() << "\n"; in runTargetDesc()
1680 OS << "static const MCPhysReg " << CSRSet->getName() << "_SaveList[] = { "; in runTargetDesc()
1707 OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { "; in runTargetDesc()
1718 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1733 if (Category.getName() == "GeneralPurposeRegisters") { in runTargetDesc()
1747 if (Category.getName() == "FixedRegisters") { in runTargetDesc()
1761 if (Category.getName() == "ArgumentRegisters") { in runTargetDesc()
1784 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1832 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1848 OS << " " << R->getName(); in debugDump()
1856 OS << " " << SRC.getName(); in debugDump()
1861 OS << " " << SRC->getName(); in debugDump()
1867 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1880 OS << "Register " << R.getName() << ":\n"; in debugDump()
1889 OS << "\tSubReg " << P.first->getName() << " = " << P.second->getName() in debugDump()