Lines Matching refs:OS
71 void runEnums(raw_ostream &OS);
74 void runMCDesc(raw_ostream &OS);
77 void runTargetHeader(raw_ostream &OS);
80 void runTargetDesc(raw_ostream &OS);
83 void run(raw_ostream &OS);
85 void debugDump(raw_ostream &OS);
88 void EmitRegMapping(raw_ostream &OS, const std::deque<CodeGenRegister> &Regs,
90 void EmitRegMappingTables(raw_ostream &OS,
93 void EmitRegUnitPressure(raw_ostream &OS, StringRef ClassName);
94 void emitComposeSubRegIndices(raw_ostream &OS, StringRef ClassName);
95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, StringRef ClassName);
101 void RegisterInfoEmitter::runEnums(raw_ostream &OS) { in runEnums() argument
109 emitSourceFileHeader("Target Register Enum Values", OS); in runEnums()
111 OS << "\n#ifdef GET_REGINFO_ENUM\n"; in runEnums()
112 OS << "#undef GET_REGINFO_ENUM\n\n"; in runEnums()
114 OS << "namespace llvm {\n\n"; in runEnums()
116 OS << "class MCRegisterClass;\n" in runEnums()
121 OS << "namespace " << Namespace << " {\n"; in runEnums()
122 OS << "enum : unsigned {\n NoRegister,\n"; in runEnums()
125 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
128 OS << " NUM_TARGET_REGS // " << Registers.size() + 1 << "\n"; in runEnums()
129 OS << "};\n"; in runEnums()
131 OS << "} // end namespace " << Namespace << "\n"; in runEnums()
140 OS << "\n// Register classes\n\n"; in runEnums()
142 OS << "namespace " << Namespace << " {\n"; in runEnums()
143 OS << "enum {\n"; in runEnums()
145 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n"; in runEnums()
146 OS << "\n};\n"; in runEnums()
148 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
155 OS << "\n// Register alternate name indices\n\n"; in runEnums()
157 OS << "namespace " << Namespace << " {\n"; in runEnums()
158 OS << "enum {\n"; in runEnums()
160 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
161 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
162 OS << "};\n"; in runEnums()
164 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
169 OS << "\n// Subregister indices\n\n"; in runEnums()
172 OS << "namespace " << Namespace << " {\n"; in runEnums()
173 OS << "enum : uint16_t {\n NoSubRegister,\n"; in runEnums()
176 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
177 OS << " NUM_TARGET_SUBREGS\n};\n"; in runEnums()
179 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
182 OS << "// Register pressure sets enum.\n"; in runEnums()
184 OS << "namespace " << Namespace << " {\n"; in runEnums()
185 OS << "enum RegisterPressureSets {\n"; in runEnums()
189 OS << " " << RegUnits.Name << " = " << i << ",\n"; in runEnums()
191 OS << "};\n"; in runEnums()
193 OS << "} // end namespace " << Namespace << '\n'; in runEnums()
194 OS << '\n'; in runEnums()
196 OS << "} // end namespace llvm\n\n"; in runEnums()
197 OS << "#endif // GET_REGINFO_ENUM\n\n"; in runEnums()
200 static void printInt(raw_ostream &OS, int Val) { OS << Val; } in printInt() argument
202 void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS, in EmitRegUnitPressure() argument
207 OS << "/// Get the weight in units of pressure for this register class.\n" in EmitRegUnitPressure()
213 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
215 OS << '0'; in EmitRegUnitPressure()
219 OS << RegBank.getRegUnitSetWeight(RegUnits); in EmitRegUnitPressure()
221 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
223 OS << " };\n" in EmitRegUnitPressure()
235 OS << "/// Get the weight in units of pressure for this register unit.\n" in EmitRegUnitPressure()
241 OS << " static const uint8_t RUWeightTable[] = {\n "; in EmitRegUnitPressure()
246 OS << RU.Weight << ", "; in EmitRegUnitPressure()
248 OS << "};\n" in EmitRegUnitPressure()
251 OS << " // All register units have unit weight.\n" in EmitRegUnitPressure()
254 OS << "}\n\n"; in EmitRegUnitPressure()
256 OS << "\n" in EmitRegUnitPressure()
261 OS << "// Get the name of this register unit pressure set.\n" in EmitRegUnitPressure()
269 OS << " \"" << RegUnits.Name << "\",\n"; in EmitRegUnitPressure()
271 OS << " };\n" in EmitRegUnitPressure()
275 OS << "// Get the register unit pressure limit for this dimension.\n" in EmitRegUnitPressure()
284 OS << " " << RegUnits.Weight << ", \t// " << i << ": " << RegUnits.Name in EmitRegUnitPressure()
287 OS << " };\n" in EmitRegUnitPressure()
310 OS << "/// Table of pressure sets per register class or unit.\n" in EmitRegUnitPressure()
312 PSetsSeqs.emit(OS, printInt); in EmitRegUnitPressure()
313 OS << "};\n\n"; in EmitRegUnitPressure()
315 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
320 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
323 OS << PSetsSeqs.get(PSets[i]) << ","; in EmitRegUnitPressure()
325 OS << "};\n" in EmitRegUnitPressure()
329 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
336 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
340 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) in EmitRegUnitPressure()
343 OS << "};\n" in EmitRegUnitPressure()
375 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
399 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; in EmitRegMappingTables()
404 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
405 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
406 OS << I << "Dwarf2L[]"; in EmitRegMappingTables()
409 OS << " = {\n"; in EmitRegMappingTables()
422 OS << " { " << I.first << "U, " << getQualifiedName(I.second) in EmitRegMappingTables()
425 OS << "};\n"; in EmitRegMappingTables()
427 OS << ";\n"; in EmitRegMappingTables()
432 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
435 OS << " = std::size(" << Namespace in EmitRegMappingTables()
438 OS << ";\n\n"; in EmitRegMappingTables()
468 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
469 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
470 OS << i << "L2Dwarf[]"; in EmitRegMappingTables()
472 OS << " = {\n"; in EmitRegMappingTables()
480 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo in EmitRegMappingTables()
483 OS << "};\n"; in EmitRegMappingTables()
485 OS << ";\n"; in EmitRegMappingTables()
490 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
493 OS << " = std::size(" << Namespace in EmitRegMappingTables()
496 OS << ";\n\n"; in EmitRegMappingTables()
502 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
519 OS << " switch ("; in EmitRegMapping()
521 OS << "DwarfFlavour"; in EmitRegMapping()
523 OS << "EHFlavour"; in EmitRegMapping()
524 OS << ") {\n" in EmitRegMapping()
529 OS << " case " << i << ":\n"; in EmitRegMapping()
530 OS << " "; in EmitRegMapping()
532 OS << "RI->"; in EmitRegMapping()
537 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
539 OS << "false"; in EmitRegMapping()
541 OS << "true"; in EmitRegMapping()
542 OS << ");\n"; in EmitRegMapping()
543 OS << " break;\n"; in EmitRegMapping()
545 OS << " }\n"; in EmitRegMapping()
550 OS << " switch ("; in EmitRegMapping()
552 OS << "DwarfFlavour"; in EmitRegMapping()
554 OS << "EHFlavour"; in EmitRegMapping()
555 OS << ") {\n" in EmitRegMapping()
560 OS << " case " << i << ":\n"; in EmitRegMapping()
561 OS << " "; in EmitRegMapping()
563 OS << "RI->"; in EmitRegMapping()
568 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
570 OS << "false"; in EmitRegMapping()
572 OS << "true"; in EmitRegMapping()
573 OS << ");\n"; in EmitRegMapping()
574 OS << " break;\n"; in EmitRegMapping()
576 OS << " }\n"; in EmitRegMapping()
582 static void printBitVectorAsHex(raw_ostream &OS, const BitVector &Bits, in printBitVectorAsHex() argument
590 OS << format("0x%0*x, ", Digits, Value); in printBitVectorAsHex()
605 void print(raw_ostream &OS) { printBitVectorAsHex(OS, Values, 8); } in print() argument
608 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { in printSimpleValueType() argument
609 OS << getEnumName(VT); in printSimpleValueType()
612 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { in printSubRegIndex() argument
613 OS << (Idx ? Idx->EnumValue : 0); in printSubRegIndex()
654 static void printDiff16(raw_ostream &OS, int16_t Val) { OS << Val; } in printDiff16() argument
656 static void printMask(raw_ostream &OS, LaneBitmask Val) { in printMask() argument
657 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; in printMask()
680 void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, in emitComposeSubRegIndices() argument
714 OS << "unsigned " << ClassName in emitComposeSubRegIndices()
719 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) in emitComposeSubRegIndices()
722 OS << RowMap[i] << ", "; in emitComposeSubRegIndices()
723 OS << "\n };\n"; in emitComposeSubRegIndices()
727 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) in emitComposeSubRegIndices()
730 OS << " { "; in emitComposeSubRegIndices()
734 OS << Elem->getQualifiedName() << ", "; in emitComposeSubRegIndices()
736 OS << "0, "; in emitComposeSubRegIndices()
737 OS << "},\n"; in emitComposeSubRegIndices()
739 OS << " };\n\n"; in emitComposeSubRegIndices()
741 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n" in emitComposeSubRegIndices()
744 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; in emitComposeSubRegIndices()
746 OS << " return Rows[0][IdxB];\n"; in emitComposeSubRegIndices()
747 OS << "}\n\n"; in emitComposeSubRegIndices()
753 OS << "unsigned " << ClassName in emitComposeSubRegIndices()
756 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) in emitComposeSubRegIndices()
762 OS << " { "; in emitComposeSubRegIndices()
780 OS << FoundReverse->getQualifiedName() << ", "; in emitComposeSubRegIndices()
782 OS << "0, "; in emitComposeSubRegIndices()
785 OS << "},\n"; in emitComposeSubRegIndices()
788 OS << " };\n\n"; in emitComposeSubRegIndices()
789 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" in emitComposeSubRegIndices()
791 OS << " return Table[IdxA][IdxB];\n"; in emitComposeSubRegIndices()
792 OS << " }\n\n"; in emitComposeSubRegIndices()
795 void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, in emitComposeSubRegIndexLaneMask() argument
825 OS << " struct MaskRolOp {\n" in emitComposeSubRegIndexLaneMask()
832 OS << " "; in emitComposeSubRegIndexLaneMask()
835 printMask(OS << "{ ", P.Mask); in emitComposeSubRegIndexLaneMask()
836 OS << format(", %2u }, ", P.RotateLeft); in emitComposeSubRegIndexLaneMask()
838 OS << "{ LaneBitmask::getNone(), 0 }"; in emitComposeSubRegIndexLaneMask()
840 OS << ", "; in emitComposeSubRegIndexLaneMask()
841 OS << " // Sequence " << Idx << "\n"; in emitComposeSubRegIndexLaneMask()
846 OS << " };\n" in emitComposeSubRegIndexLaneMask()
850 OS << " "; in emitComposeSubRegIndexLaneMask()
851 OS << SubReg2SequenceIndexMap[i]; in emitComposeSubRegIndexLaneMask()
853 OS << ","; in emitComposeSubRegIndexLaneMask()
854 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
856 OS << " };\n\n"; in emitComposeSubRegIndexLaneMask()
858 OS << "LaneBitmask " << ClassName in emitComposeSubRegIndexLaneMask()
879 OS << "LaneBitmask " << ClassName in emitComposeSubRegIndexLaneMask()
904 void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) { in runMCDesc() argument
905 emitSourceFileHeader("MC Register Information", OS); in runMCDesc()
907 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; in runMCDesc()
908 OS << "#undef GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
975 OS << "namespace llvm {\n\n"; in runMCDesc()
980 OS << "extern const int16_t " << TargetName << "RegDiffLists[] = {\n"; in runMCDesc()
981 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
982 OS << "};\n\n"; in runMCDesc()
985 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; in runMCDesc()
986 LaneMaskSeqs.emit(OS, printMask); in runMCDesc()
987 OS << "};\n\n"; in runMCDesc()
990 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; in runMCDesc()
991 SubRegIdxSeqs.emit(OS, printSubRegIndex); in runMCDesc()
992 OS << "};\n\n"; in runMCDesc()
996 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName + in runMCDesc()
999 OS << "extern const MCRegisterDesc " << TargetName in runMCDesc()
1001 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0, 0, 0 },\n"; in runMCDesc()
1012 OS << " { " << RegStrings.get(Reg.getName().str()) << ", " in runMCDesc()
1020 OS << "};\n\n"; // End of register descriptors... in runMCDesc()
1024 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; in runMCDesc()
1029 OS << " { "; in runMCDesc()
1032 OS << LS << getQualifiedName(R->TheDef); in runMCDesc()
1033 OS << " },\n"; in runMCDesc()
1035 OS << "};\n\n"; in runMCDesc()
1040 OS << "namespace { // Register classes...\n"; in runMCDesc()
1055 OS << " // " << Name << " Register Class...\n" in runMCDesc()
1058 OS << getQualifiedName(Reg) << ", "; in runMCDesc()
1060 OS << "\n };\n\n"; in runMCDesc()
1062 OS << " // " << Name << " Bit set.\n" in runMCDesc()
1068 BVE.print(OS); in runMCDesc()
1069 OS << "\n };\n\n"; in runMCDesc()
1072 OS << "} // end anonymous namespace\n\n"; in runMCDesc()
1076 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]"); in runMCDesc()
1078 OS << "extern const MCRegisterClass " << TargetName in runMCDesc()
1090 OS << " { " << RCName << ", " << RCBitsName << ", " in runMCDesc()
1098 OS << "};\n\n"; in runMCDesc()
1100 EmitRegMappingTables(OS, Regs, false); in runMCDesc()
1103 OS << "extern const uint16_t " << TargetName; in runMCDesc()
1104 OS << "RegEncodingTable[] = {\n"; in runMCDesc()
1106 OS << " 0,\n"; in runMCDesc()
1115 OS << " " << Value << ",\n"; in runMCDesc()
1117 OS << "};\n"; // End of HW encoding table in runMCDesc()
1120 OS << "static inline void Init" << TargetName in runMCDesc()
1133 EmitRegMapping(OS, Regs, false); in runMCDesc()
1135 OS << "}\n\n"; in runMCDesc()
1137 OS << "} // end namespace llvm\n\n"; in runMCDesc()
1138 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
1141 void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS) { in runTargetHeader() argument
1142 emitSourceFileHeader("Register Information Header Fragment", OS); in runTargetHeader()
1144 OS << "\n#ifdef GET_REGINFO_HEADER\n"; in runTargetHeader()
1145 OS << "#undef GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1150 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; in runTargetHeader()
1152 OS << "namespace llvm {\n\n"; in runTargetHeader()
1154 OS << "class " << TargetName << "FrameLowering;\n\n"; in runTargetHeader()
1156 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" in runTargetHeader()
1161 OS << " unsigned composeSubRegIndicesImpl" in runTargetHeader()
1174 OS << " const RegClassWeight &getRegClassWeight(" in runTargetHeader()
1203 OS << " const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) " in runTargetHeader()
1207 OS << "};\n\n"; in runTargetHeader()
1210 OS << "namespace " << RegisterClasses.front().Namespace in runTargetHeader()
1217 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; in runTargetHeader()
1219 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; in runTargetHeader()
1221 OS << "} // end namespace llvm\n\n"; in runTargetHeader()
1222 OS << "#endif // GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1228 void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) { in runTargetDesc() argument
1229 emitSourceFileHeader("Target Register and Register Classes Information", OS); in runTargetDesc()
1231 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1232 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1234 OS << "namespace llvm {\n\n"; in runTargetDesc()
1237 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1271 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; in runTargetDesc()
1272 VTSeqs.emit(OS, printSimpleValueType); in runTargetDesc()
1273 OS << "};\n"; in runTargetDesc()
1276 OS << "\nstatic const char *SubRegIndexNameTable[] = { \""; in runTargetDesc()
1279 OS << Idx.getName(); in runTargetDesc()
1280 OS << "\", \""; in runTargetDesc()
1282 OS << "\" };\n\n"; in runTargetDesc()
1285 OS << "static const TargetRegisterInfo::SubRegCoveredBits " in runTargetDesc()
1288 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; in runTargetDesc()
1291 OS << " { " << Range.Offset << ", " << Range.Size << " },\t// " in runTargetDesc()
1295 OS << "};\n\n"; in runTargetDesc()
1298 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " in runTargetDesc()
1301 printMask(OS << " ", Idx.LaneMask); in runTargetDesc()
1302 OS << ", // " << Idx.getName() << '\n'; in runTargetDesc()
1304 OS << " };\n\n"; in runTargetDesc()
1306 OS << "\n"; in runTargetDesc()
1310 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" in runTargetDesc()
1314 OS << " // Mode = " << M << " ("; in runTargetDesc()
1316 OS << "Default"; in runTargetDesc()
1318 OS << CGH.getMode(M).Name; in runTargetDesc()
1319 OS << ")\n"; in runTargetDesc()
1325 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
1331 OS << ", /*VTLists+*/" << VTSeqs.get(VTs) << " }, // " in runTargetDesc()
1335 OS << "};\n"; in runTargetDesc()
1362 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1364 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1375 OS << "\n "; in runTargetDesc()
1376 printBitVectorAsHex(OS, MaskBV, 32); in runTargetDesc()
1377 OS << "// " << Idx.getName(); in runTargetDesc()
1380 OS << "\n};\n\n"; in runTargetDesc()
1383 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; in runTargetDesc()
1385 SuperRegIdxSeqs.emit(OS, printSubRegIndex); in runTargetDesc()
1386 OS << "};\n\n"; in runTargetDesc()
1396 OS << "static unsigned const " << RC.getName() << "Superclasses[] = {\n"; in runTargetDesc()
1398 OS << " " << Super->getQualifiedIdName() << ",\n"; in runTargetDesc()
1399 OS << "};\n\n"; in runTargetDesc()
1405 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1413 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; in runTargetDesc()
1415 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); in runTargetDesc()
1416 OS << " };\n"; in runTargetDesc()
1419 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1425 OS << "),\n ArrayRef<MCPhysReg>("; in runTargetDesc()
1427 OS << "),\n ArrayRef(AltOrder" << oi; in runTargetDesc()
1428 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1435 OS << "\nnamespace " << RegisterClasses.front().Namespace in runTargetDesc()
1439 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1444 printMask(OS, RC.LaneMask); in runTargetDesc()
1445 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " in runTargetDesc()
1453 OS << "nullptr, "; in runTargetDesc()
1455 OS << RC.getName() << "Superclasses, "; in runTargetDesc()
1456 OS << RC.getSuperClasses().size() << ",\n "; in runTargetDesc()
1458 OS << "nullptr\n"; in runTargetDesc()
1460 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1461 OS << " };\n\n"; in runTargetDesc()
1464 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; in runTargetDesc()
1467 OS << "\nnamespace {\n"; in runTargetDesc()
1468 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; in runTargetDesc()
1470 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1471 OS << " };\n"; in runTargetDesc()
1472 OS << "} // end anonymous namespace\n"; in runTargetDesc()
1502 OS << "\nstatic const uint8_t " in runTargetDesc()
1506 OS << AllRegCostPerUse[J] << ", "; in runTargetDesc()
1508 OS << "};\n\n"; in runTargetDesc()
1510 OS << "\nstatic const bool " in runTargetDesc()
1513 OS << (InAllocClass[I] ? "true" : "false") << ", "; in runTargetDesc()
1515 OS << "};\n\n"; in runTargetDesc()
1517 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName in runTargetDesc()
1519 OS << "CostPerUseTable, " << NumRegCosts << ", " in runTargetDesc()
1521 OS << "};\n\n"; // End of register descriptors... in runTargetDesc()
1529 emitComposeSubRegIndices(OS, ClassName); in runTargetDesc()
1530 emitComposeSubRegIndexLaneMask(OS, ClassName); in runTargetDesc()
1535 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1541 OS << " static const uint8_t Table["; in runTargetDesc()
1543 OS << " static const uint16_t Table["; in runTargetDesc()
1546 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1548 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1551 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1554 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1556 OS << " },\n"; in runTargetDesc()
1558 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1565 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1572 OS << " static const uint8_t Table["; in runTargetDesc()
1574 OS << " static const uint16_t Table["; in runTargetDesc()
1578 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1581 OS << " {\t// " << RC.getName() << '\n'; in runTargetDesc()
1592 OS << " " << EnumValue << ",\t// " << RC.getName() << ':' in runTargetDesc()
1597 OS << " -> " << SubRegClass->getName(); in runTargetDesc()
1600 OS << '\n'; in runTargetDesc()
1603 OS << " },\n"; in runTargetDesc()
1605 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1612 EmitRegUnitPressure(OS, ClassName); in runTargetDesc()
1636 OS << "\n// Register to base register class mapping\n\n"; in runTargetDesc()
1637 OS << "\n"; in runTargetDesc()
1638 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1641 OS << " static const uint16_t InvalidRegClassID = UINT16_MAX;\n\n"; in runTargetDesc()
1642 OS << " static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n"; in runTargetDesc()
1643 OS << " InvalidRegClassID, // NoRegister\n"; in runTargetDesc()
1653 OS << " " in runTargetDesc()
1657 OS << " };\n\n" in runTargetDesc()
1668 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; in runTargetDesc()
1669 OS << "extern const int16_t " << TargetName << "RegDiffLists[];\n"; in runTargetDesc()
1670 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; in runTargetDesc()
1671 OS << "extern const char " << TargetName << "RegStrings[];\n"; in runTargetDesc()
1672 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; in runTargetDesc()
1673 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; in runTargetDesc()
1674 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; in runTargetDesc()
1675 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; in runTargetDesc()
1677 EmitRegMappingTables(OS, Regs, true); in runTargetDesc()
1679 OS << ClassName << "::\n" in runTargetDesc()
1688 printMask(OS, RegBank.CoveringLanes); in runTargetDesc()
1689 OS << ", RegClassInfos, VTLists, HwMode) {\n" in runTargetDesc()
1703 EmitRegMapping(OS, Regs, true); in runTargetDesc()
1705 OS << "}\n\n"; in runTargetDesc()
1715 OS << "static const MCPhysReg " << CSRSet->getName() << "_SaveList[] = { "; in runTargetDesc()
1717 OS << getQualifiedName(Reg) << ", "; in runTargetDesc()
1718 OS << "0 };\n"; in runTargetDesc()
1740 OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { "; in runTargetDesc()
1741 printBitVectorAsHex(OS, Covered, 32); in runTargetDesc()
1742 OS << "};\n"; in runTargetDesc()
1744 OS << "\n\n"; in runTargetDesc()
1746 OS << "ArrayRef<const uint32_t *> " << ClassName in runTargetDesc()
1749 OS << " static const uint32_t *const Masks[] = {\n"; in runTargetDesc()
1751 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1752 OS << " };\n"; in runTargetDesc()
1753 OS << " return ArrayRef(Masks);\n"; in runTargetDesc()
1755 OS << " return {};\n"; in runTargetDesc()
1757 OS << "}\n\n"; in runTargetDesc()
1761 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1768 OS << " " << RC->getQualifiedName() in runTargetDesc()
1772 OS << " false;\n"; in runTargetDesc()
1773 OS << "}\n\n"; in runTargetDesc()
1775 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1782 OS << " " << RC->getQualifiedName() in runTargetDesc()
1786 OS << " false;\n"; in runTargetDesc()
1787 OS << "}\n\n"; in runTargetDesc()
1789 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1796 OS << " " << RC->getQualifiedName() in runTargetDesc()
1800 OS << " false;\n"; in runTargetDesc()
1801 OS << "}\n\n"; in runTargetDesc()
1803 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1810 OS << " " << RC->getQualifiedName() in runTargetDesc()
1814 OS << " false;\n"; in runTargetDesc()
1815 OS << "}\n\n"; in runTargetDesc()
1817 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1822 OS << " PhysReg == " << getQualifiedName(Reg.TheDef) << " ||\n"; in runTargetDesc()
1823 OS << " false;\n"; in runTargetDesc()
1824 OS << "}\n\n"; in runTargetDesc()
1826 OS << "ArrayRef<const char *> " << ClassName in runTargetDesc()
1829 OS << " static const char *Names[] = {\n"; in runTargetDesc()
1831 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1832 OS << " };\n"; in runTargetDesc()
1833 OS << " return ArrayRef(Names);\n"; in runTargetDesc()
1835 OS << " return {};\n"; in runTargetDesc()
1837 OS << "}\n\n"; in runTargetDesc()
1839 OS << "const " << TargetName << "FrameLowering *\n" in runTargetDesc()
1846 OS << "} // end namespace llvm\n\n"; in runTargetDesc()
1847 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1850 void RegisterInfoEmitter::run(raw_ostream &OS) { in run() argument
1853 runEnums(OS); in run()
1856 runMCDesc(OS); in run()
1859 runTargetHeader(OS); in run()
1862 runTargetDesc(OS); in run()
1868 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { in debugDump() argument
1878 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1879 OS << "\tSpillSize: {"; in debugDump()
1881 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; in debugDump()
1882 OS << " }\n\tSpillAlignment: {"; in debugDump()
1884 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; in debugDump()
1885 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; in debugDump()
1886 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; in debugDump()
1887 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; in debugDump()
1888 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; in debugDump()
1889 OS << "\tAllocatable: " << RC.Allocatable << '\n'; in debugDump()
1890 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n'; in debugDump()
1891 OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n'; in debugDump()
1892 OS << "\tRegs:"; in debugDump()
1894 OS << " " << R->getName(); in debugDump()
1896 OS << '\n'; in debugDump()
1897 OS << "\tSubClasses:"; in debugDump()
1902 OS << " " << SRC.getName(); in debugDump()
1904 OS << '\n'; in debugDump()
1905 OS << "\tSuperClasses:"; in debugDump()
1907 OS << " " << SRC->getName(); in debugDump()
1909 OS << '\n'; in debugDump()
1913 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1914 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump()
1915 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; in debugDump()
1916 OS << "\tOffset: {"; in debugDump()
1918 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Offset; in debugDump()
1919 OS << " }\n\tSize: {"; in debugDump()
1921 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Size; in debugDump()
1922 OS << " }\n"; in debugDump()
1926 OS << "Register " << R.getName() << ":\n"; in debugDump()
1927 OS << "\tCostPerUse: "; in debugDump()
1929 OS << Cost << " "; in debugDump()
1930 OS << '\n'; in debugDump()
1931 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; in debugDump()
1932 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; in debugDump()
1934 OS << "\tSubReg " << SubIdx->getName() << " = " << SubReg->getName() in debugDump()
1938 OS << "\tRegUnit " << U << '\n'; in debugDump()