Lines Matching refs:OS
85 void debugDump(raw_ostream &OS);
93 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
95 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
97 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
104 void RegisterInfoEmitter::runEnums(raw_ostream &OS, CodeGenTarget &Target, in runEnums() argument
113 emitSourceFileHeader("Target Register Enum Values", OS); in runEnums()
115 OS << "\n#ifdef GET_REGINFO_ENUM\n"; in runEnums()
116 OS << "#undef GET_REGINFO_ENUM\n\n"; in runEnums()
118 OS << "namespace llvm {\n\n"; in runEnums()
120 OS << "class MCRegisterClass;\n" in runEnums()
125 OS << "namespace " << Namespace << " {\n"; in runEnums()
126 OS << "enum {\n NoRegister,\n"; in runEnums()
129 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
132 OS << " NUM_TARGET_REGS // " << Registers.size() + 1 << "\n"; in runEnums()
133 OS << "};\n"; in runEnums()
135 OS << "} // end namespace " << Namespace << "\n"; in runEnums()
144 OS << "\n// Register classes\n\n"; in runEnums()
146 OS << "namespace " << Namespace << " {\n"; in runEnums()
147 OS << "enum {\n"; in runEnums()
149 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n"; in runEnums()
150 OS << "\n};\n"; in runEnums()
152 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
160 OS << "\n// Register alternate name indices\n\n"; in runEnums()
162 OS << "namespace " << Namespace << " {\n"; in runEnums()
163 OS << "enum {\n"; in runEnums()
165 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
166 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
167 OS << "};\n"; in runEnums()
169 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
174 OS << "\n// Subregister indices\n\n"; in runEnums()
177 OS << "namespace " << Namespace << " {\n"; in runEnums()
178 OS << "enum : uint16_t {\n NoSubRegister,\n"; in runEnums()
181 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
182 OS << " NUM_TARGET_SUBREGS\n};\n"; in runEnums()
184 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
187 OS << "// Register pressure sets enum.\n"; in runEnums()
189 OS << "namespace " << Namespace << " {\n"; in runEnums()
190 OS << "enum RegisterPressureSets {\n"; in runEnums()
194 OS << " " << RegUnits.Name << " = " << i << ",\n"; in runEnums()
196 OS << "};\n"; in runEnums()
198 OS << "} // end namespace " << Namespace << '\n'; in runEnums()
199 OS << '\n'; in runEnums()
201 OS << "} // end namespace llvm\n\n"; in runEnums()
202 OS << "#endif // GET_REGINFO_ENUM\n\n"; in runEnums()
205 static void printInt(raw_ostream &OS, int Val) { OS << Val; } in printInt() argument
207 void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS, in EmitRegUnitPressure() argument
213 OS << "/// Get the weight in units of pressure for this register class.\n" in EmitRegUnitPressure()
219 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
221 OS << '0'; in EmitRegUnitPressure()
225 OS << RegBank.getRegUnitSetWeight(RegUnits); in EmitRegUnitPressure()
227 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
229 OS << " };\n" in EmitRegUnitPressure()
241 OS << "/// Get the weight in units of pressure for this register unit.\n" in EmitRegUnitPressure()
247 OS << " static const uint8_t RUWeightTable[] = {\n "; in EmitRegUnitPressure()
252 OS << RU.Weight << ", "; in EmitRegUnitPressure()
254 OS << "};\n" in EmitRegUnitPressure()
257 OS << " // All register units have unit weight.\n" in EmitRegUnitPressure()
260 OS << "}\n\n"; in EmitRegUnitPressure()
262 OS << "\n" in EmitRegUnitPressure()
267 OS << "// Get the name of this register unit pressure set.\n" in EmitRegUnitPressure()
275 OS << " \"" << RegUnits.Name << "\",\n"; in EmitRegUnitPressure()
277 OS << " };\n" in EmitRegUnitPressure()
281 OS << "// Get the register unit pressure limit for this dimension.\n" in EmitRegUnitPressure()
290 OS << " " << RegUnits.Weight << ", \t// " << i << ": " << RegUnits.Name in EmitRegUnitPressure()
293 OS << " };\n" in EmitRegUnitPressure()
316 OS << "/// Table of pressure sets per register class or unit.\n" in EmitRegUnitPressure()
318 PSetsSeqs.emit(OS, printInt, "-1"); in EmitRegUnitPressure()
319 OS << "};\n\n"; in EmitRegUnitPressure()
321 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
326 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
329 OS << PSetsSeqs.get(PSets[i]) << ","; in EmitRegUnitPressure()
331 OS << "};\n" in EmitRegUnitPressure()
335 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
342 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
346 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) in EmitRegUnitPressure()
349 OS << "};\n" in EmitRegUnitPressure()
381 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
405 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; in EmitRegMappingTables()
410 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
411 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
412 OS << I << "Dwarf2L[]"; in EmitRegMappingTables()
415 OS << " = {\n"; in EmitRegMappingTables()
428 OS << " { " << I.first << "U, " << getQualifiedName(I.second) in EmitRegMappingTables()
431 OS << "};\n"; in EmitRegMappingTables()
433 OS << ";\n"; in EmitRegMappingTables()
438 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
441 OS << " = std::size(" << Namespace in EmitRegMappingTables()
444 OS << ";\n\n"; in EmitRegMappingTables()
474 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
475 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
476 OS << i << "L2Dwarf[]"; in EmitRegMappingTables()
478 OS << " = {\n"; in EmitRegMappingTables()
486 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo in EmitRegMappingTables()
489 OS << "};\n"; in EmitRegMappingTables()
491 OS << ";\n"; in EmitRegMappingTables()
496 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
499 OS << " = std::size(" << Namespace in EmitRegMappingTables()
502 OS << ";\n\n"; in EmitRegMappingTables()
508 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
525 OS << " switch ("; in EmitRegMapping()
527 OS << "DwarfFlavour"; in EmitRegMapping()
529 OS << "EHFlavour"; in EmitRegMapping()
530 OS << ") {\n" in EmitRegMapping()
535 OS << " case " << i << ":\n"; in EmitRegMapping()
536 OS << " "; in EmitRegMapping()
538 OS << "RI->"; in EmitRegMapping()
543 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
545 OS << "false"; in EmitRegMapping()
547 OS << "true"; in EmitRegMapping()
548 OS << ");\n"; in EmitRegMapping()
549 OS << " break;\n"; in EmitRegMapping()
551 OS << " }\n"; in EmitRegMapping()
556 OS << " switch ("; in EmitRegMapping()
558 OS << "DwarfFlavour"; in EmitRegMapping()
560 OS << "EHFlavour"; in EmitRegMapping()
561 OS << ") {\n" in EmitRegMapping()
566 OS << " case " << i << ":\n"; in EmitRegMapping()
567 OS << " "; in EmitRegMapping()
569 OS << "RI->"; in EmitRegMapping()
574 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
576 OS << "false"; in EmitRegMapping()
578 OS << "true"; in EmitRegMapping()
579 OS << ");\n"; in EmitRegMapping()
580 OS << " break;\n"; in EmitRegMapping()
582 OS << " }\n"; in EmitRegMapping()
588 static void printBitVectorAsHex(raw_ostream &OS, const BitVector &Bits, in printBitVectorAsHex() argument
596 OS << format("0x%0*x, ", Digits, Value); in printBitVectorAsHex()
611 void print(raw_ostream &OS) { printBitVectorAsHex(OS, Values, 8); } in print() argument
614 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { in printSimpleValueType() argument
615 OS << getEnumName(VT); in printSimpleValueType()
618 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { in printSubRegIndex() argument
619 OS << Idx->EnumValue; in printSubRegIndex()
660 static void printDiff16(raw_ostream &OS, int16_t Val) { OS << Val; } in printDiff16() argument
662 static void printMask(raw_ostream &OS, LaneBitmask Val) { in printMask() argument
663 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; in printMask()
686 void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, in emitComposeSubRegIndices() argument
690 OS << "unsigned " << ClName in emitComposeSubRegIndices()
725 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) in emitComposeSubRegIndices()
728 OS << RowMap[i] << ", "; in emitComposeSubRegIndices()
729 OS << "\n };\n"; in emitComposeSubRegIndices()
733 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) in emitComposeSubRegIndices()
736 OS << " { "; in emitComposeSubRegIndices()
739 OS << Rows[r][i]->getQualifiedName() << ", "; in emitComposeSubRegIndices()
741 OS << "0, "; in emitComposeSubRegIndices()
742 OS << "},\n"; in emitComposeSubRegIndices()
744 OS << " };\n\n"; in emitComposeSubRegIndices()
746 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n" in emitComposeSubRegIndices()
749 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; in emitComposeSubRegIndices()
751 OS << " return Rows[0][IdxB];\n"; in emitComposeSubRegIndices()
752 OS << "}\n\n"; in emitComposeSubRegIndices()
756 raw_ostream &OS, CodeGenRegBank &RegBank, const std::string &ClName) { in emitComposeSubRegIndexLaneMask() argument
785 OS << " struct MaskRolOp {\n" in emitComposeSubRegIndexLaneMask()
792 OS << " "; in emitComposeSubRegIndexLaneMask()
796 printMask(OS << "{ ", P.Mask); in emitComposeSubRegIndexLaneMask()
797 OS << format(", %2u }, ", P.RotateLeft); in emitComposeSubRegIndexLaneMask()
799 OS << "{ LaneBitmask::getNone(), 0 }"; in emitComposeSubRegIndexLaneMask()
801 OS << ", "; in emitComposeSubRegIndexLaneMask()
802 OS << " // Sequence " << Idx << "\n"; in emitComposeSubRegIndexLaneMask()
807 OS << " };\n" in emitComposeSubRegIndexLaneMask()
811 OS << " "; in emitComposeSubRegIndexLaneMask()
812 OS << SubReg2SequenceIndexMap[i]; in emitComposeSubRegIndexLaneMask()
814 OS << ","; in emitComposeSubRegIndexLaneMask()
815 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
817 OS << " };\n\n"; in emitComposeSubRegIndexLaneMask()
819 OS << "LaneBitmask " << ClName in emitComposeSubRegIndexLaneMask()
840 OS << "LaneBitmask " << ClName in emitComposeSubRegIndexLaneMask()
865 void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, in runMCDesc() argument
867 emitSourceFileHeader("MC Register Information", OS); in runMCDesc()
869 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; in runMCDesc()
870 OS << "#undef GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
936 OS << "namespace llvm {\n\n"; in runMCDesc()
941 OS << "extern const int16_t " << TargetName << "RegDiffLists[] = {\n"; in runMCDesc()
942 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
943 OS << "};\n\n"; in runMCDesc()
946 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; in runMCDesc()
949 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); in runMCDesc()
950 OS << "};\n\n"; in runMCDesc()
953 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; in runMCDesc()
954 SubRegIdxSeqs.emit(OS, printSubRegIndex); in runMCDesc()
955 OS << "};\n\n"; in runMCDesc()
959 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName + in runMCDesc()
962 OS << "extern const MCRegisterDesc " << TargetName in runMCDesc()
964 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0, 0 },\n"; in runMCDesc()
975 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", " in runMCDesc()
983 OS << "};\n\n"; // End of register descriptors... in runMCDesc()
987 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; in runMCDesc()
992 OS << " { "; in runMCDesc()
995 OS << LS << getQualifiedName(R->TheDef); in runMCDesc()
996 OS << " },\n"; in runMCDesc()
998 OS << "};\n\n"; in runMCDesc()
1003 OS << "namespace { // Register classes...\n"; in runMCDesc()
1018 OS << " // " << Name << " Register Class...\n" in runMCDesc()
1021 OS << getQualifiedName(Reg) << ", "; in runMCDesc()
1023 OS << "\n };\n\n"; in runMCDesc()
1025 OS << " // " << Name << " Bit set.\n" in runMCDesc()
1031 BVE.print(OS); in runMCDesc()
1032 OS << "\n };\n\n"; in runMCDesc()
1035 OS << "} // end anonymous namespace\n\n"; in runMCDesc()
1039 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]"); in runMCDesc()
1041 OS << "extern const MCRegisterClass " << TargetName in runMCDesc()
1053 OS << " { " << RCName << ", " << RCBitsName << ", " in runMCDesc()
1061 OS << "};\n\n"; in runMCDesc()
1063 EmitRegMappingTables(OS, Regs, false); in runMCDesc()
1066 OS << "extern const uint16_t " << TargetName; in runMCDesc()
1067 OS << "RegEncodingTable[] = {\n"; in runMCDesc()
1069 OS << " 0,\n"; in runMCDesc()
1078 OS << " " << Value << ",\n"; in runMCDesc()
1080 OS << "};\n"; // End of HW encoding table in runMCDesc()
1083 OS << "static inline void Init" << TargetName in runMCDesc()
1096 EmitRegMapping(OS, Regs, false); in runMCDesc()
1098 OS << "}\n\n"; in runMCDesc()
1100 OS << "} // end namespace llvm\n\n"; in runMCDesc()
1101 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
1104 void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, in runTargetHeader() argument
1107 emitSourceFileHeader("Register Information Header Fragment", OS); in runTargetHeader()
1109 OS << "\n#ifdef GET_REGINFO_HEADER\n"; in runTargetHeader()
1110 OS << "#undef GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1115 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; in runTargetHeader()
1117 OS << "namespace llvm {\n\n"; in runTargetHeader()
1119 OS << "class " << TargetName << "FrameLowering;\n\n"; in runTargetHeader()
1121 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" in runTargetHeader()
1126 OS << " unsigned composeSubRegIndicesImpl" in runTargetHeader()
1137 OS << " const RegClassWeight &getRegClassWeight(" in runTargetHeader()
1164 OS << " const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) " in runTargetHeader()
1168 OS << "};\n\n"; in runTargetHeader()
1171 OS << "namespace " << RegisterClasses.front().Namespace in runTargetHeader()
1178 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; in runTargetHeader()
1180 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; in runTargetHeader()
1182 OS << "} // end namespace llvm\n\n"; in runTargetHeader()
1183 OS << "#endif // GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1189 void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, in runTargetDesc() argument
1191 emitSourceFileHeader("Target Register and Register Classes Information", OS); in runTargetDesc()
1193 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1194 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1196 OS << "namespace llvm {\n\n"; in runTargetDesc()
1199 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1232 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; in runTargetDesc()
1233 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); in runTargetDesc()
1234 OS << "};\n"; in runTargetDesc()
1237 OS << "\nstatic const char *SubRegIndexNameTable[] = { \""; in runTargetDesc()
1240 OS << Idx.getName(); in runTargetDesc()
1241 OS << "\", \""; in runTargetDesc()
1243 OS << "\" };\n\n"; in runTargetDesc()
1246 OS << "static const TargetRegisterInfo::SubRegCoveredBits " in runTargetDesc()
1249 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; in runTargetDesc()
1252 OS << " { " << Range.Offset << ", " << Range.Size << " },\t// " in runTargetDesc()
1256 OS << "};\n\n"; in runTargetDesc()
1259 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " in runTargetDesc()
1262 printMask(OS << " ", Idx.LaneMask); in runTargetDesc()
1263 OS << ", // " << Idx.getName() << '\n'; in runTargetDesc()
1265 OS << " };\n\n"; in runTargetDesc()
1267 OS << "\n"; in runTargetDesc()
1271 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" in runTargetDesc()
1275 OS << " // Mode = " << M << " ("; in runTargetDesc()
1277 OS << "Default"; in runTargetDesc()
1279 OS << CGH.getMode(M).Name; in runTargetDesc()
1280 OS << ")\n"; in runTargetDesc()
1286 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
1292 OS << ", /*VTLists+*/" << VTSeqs.get(VTs) << " }, // " in runTargetDesc()
1296 OS << "};\n"; in runTargetDesc()
1298 OS << "\nstatic const TargetRegisterClass *const " in runTargetDesc()
1326 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1328 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1339 OS << "\n "; in runTargetDesc()
1340 printBitVectorAsHex(OS, MaskBV, 32); in runTargetDesc()
1341 OS << "// " << Idx.getName(); in runTargetDesc()
1344 OS << "\n};\n\n"; in runTargetDesc()
1347 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; in runTargetDesc()
1349 SuperRegIdxSeqs.emit(OS, printSubRegIndex); in runTargetDesc()
1350 OS << "};\n\n"; in runTargetDesc()
1360 OS << "static const TargetRegisterClass *const " << RC.getName() in runTargetDesc()
1363 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1364 OS << " nullptr\n};\n\n"; in runTargetDesc()
1370 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1378 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; in runTargetDesc()
1380 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); in runTargetDesc()
1381 OS << " };\n"; in runTargetDesc()
1384 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1390 OS << "),\n ArrayRef<MCPhysReg>("; in runTargetDesc()
1392 OS << "),\n ArrayRef(AltOrder" << oi; in runTargetDesc()
1393 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1400 OS << "\nnamespace " << RegisterClasses.front().Namespace in runTargetDesc()
1404 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1409 printMask(OS, RC.LaneMask); in runTargetDesc()
1410 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " in runTargetDesc()
1418 OS << "NullRegClasses,\n "; in runTargetDesc()
1420 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1422 OS << "nullptr\n"; in runTargetDesc()
1424 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1425 OS << " };\n\n"; in runTargetDesc()
1428 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; in runTargetDesc()
1431 OS << "\nnamespace {\n"; in runTargetDesc()
1432 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; in runTargetDesc()
1434 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1435 OS << " };\n"; in runTargetDesc()
1436 OS << "} // end anonymous namespace\n"; in runTargetDesc()
1466 OS << "\nstatic const uint8_t " in runTargetDesc()
1470 OS << AllRegCostPerUse[J] << ", "; in runTargetDesc()
1472 OS << "};\n\n"; in runTargetDesc()
1474 OS << "\nstatic const bool " in runTargetDesc()
1477 OS << (InAllocClass[I] ? "true" : "false") << ", "; in runTargetDesc()
1479 OS << "};\n\n"; in runTargetDesc()
1481 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName in runTargetDesc()
1483 OS << "CostPerUseTable, " << NumRegCosts << ", " in runTargetDesc()
1485 OS << "};\n\n"; // End of register descriptors... in runTargetDesc()
1493 emitComposeSubRegIndices(OS, RegBank, ClassName); in runTargetDesc()
1494 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); in runTargetDesc()
1499 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1505 OS << " static const uint8_t Table["; in runTargetDesc()
1507 OS << " static const uint16_t Table["; in runTargetDesc()
1510 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1512 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1515 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1518 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1520 OS << " },\n"; in runTargetDesc()
1522 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1529 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1536 OS << " static const uint8_t Table["; in runTargetDesc()
1538 OS << " static const uint16_t Table["; in runTargetDesc()
1542 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1545 OS << " {\t// " << RC.getName() << '\n'; in runTargetDesc()
1556 OS << " " << EnumValue << ",\t// " << RC.getName() << ':' in runTargetDesc()
1561 OS << " -> " << SubRegClass->getName(); in runTargetDesc()
1564 OS << '\n'; in runTargetDesc()
1567 OS << " },\n"; in runTargetDesc()
1569 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1576 EmitRegUnitPressure(OS, RegBank, ClassName); in runTargetDesc()
1600 OS << "\n// Register to base register class mapping\n\n"; in runTargetDesc()
1601 OS << "\n"; in runTargetDesc()
1602 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1605 OS << " static const uint16_t InvalidRegClassID = UINT16_MAX;\n\n"; in runTargetDesc()
1606 OS << " static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n"; in runTargetDesc()
1607 OS << " InvalidRegClassID, // NoRegister\n"; in runTargetDesc()
1617 OS << " " in runTargetDesc()
1621 OS << " };\n\n" in runTargetDesc()
1632 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; in runTargetDesc()
1633 OS << "extern const int16_t " << TargetName << "RegDiffLists[];\n"; in runTargetDesc()
1634 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; in runTargetDesc()
1635 OS << "extern const char " << TargetName << "RegStrings[];\n"; in runTargetDesc()
1636 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; in runTargetDesc()
1637 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; in runTargetDesc()
1638 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; in runTargetDesc()
1639 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; in runTargetDesc()
1641 EmitRegMappingTables(OS, Regs, true); in runTargetDesc()
1643 OS << ClassName << "::\n" in runTargetDesc()
1652 printMask(OS, RegBank.CoveringLanes); in runTargetDesc()
1653 OS << ", RegClassInfos, VTLists, HwMode) {\n" in runTargetDesc()
1667 EmitRegMapping(OS, Regs, true); in runTargetDesc()
1669 OS << "}\n\n"; in runTargetDesc()
1680 OS << "static const MCPhysReg " << CSRSet->getName() << "_SaveList[] = { "; in runTargetDesc()
1682 OS << getQualifiedName((*Regs)[r]) << ", "; in runTargetDesc()
1683 OS << "0 };\n"; in runTargetDesc()
1707 OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { "; in runTargetDesc()
1708 printBitVectorAsHex(OS, Covered, 32); in runTargetDesc()
1709 OS << "};\n"; in runTargetDesc()
1711 OS << "\n\n"; in runTargetDesc()
1713 OS << "ArrayRef<const uint32_t *> " << ClassName in runTargetDesc()
1716 OS << " static const uint32_t *const Masks[] = {\n"; in runTargetDesc()
1718 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1719 OS << " };\n"; in runTargetDesc()
1720 OS << " return ArrayRef(Masks);\n"; in runTargetDesc()
1722 OS << " return std::nullopt;\n"; in runTargetDesc()
1724 OS << "}\n\n"; in runTargetDesc()
1728 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1735 OS << " " << RC->getQualifiedName() in runTargetDesc()
1739 OS << " false;\n"; in runTargetDesc()
1740 OS << "}\n\n"; in runTargetDesc()
1742 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1749 OS << " " << RC->getQualifiedName() in runTargetDesc()
1753 OS << " false;\n"; in runTargetDesc()
1754 OS << "}\n\n"; in runTargetDesc()
1756 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1763 OS << " " << RC->getQualifiedName() in runTargetDesc()
1767 OS << " false;\n"; in runTargetDesc()
1768 OS << "}\n\n"; in runTargetDesc()
1770 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1775 OS << " PhysReg == " << getQualifiedName(Reg.TheDef) << " ||\n"; in runTargetDesc()
1776 OS << " false;\n"; in runTargetDesc()
1777 OS << "}\n\n"; in runTargetDesc()
1779 OS << "ArrayRef<const char *> " << ClassName in runTargetDesc()
1782 OS << " static const char *Names[] = {\n"; in runTargetDesc()
1784 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1785 OS << " };\n"; in runTargetDesc()
1786 OS << " return ArrayRef(Names);\n"; in runTargetDesc()
1788 OS << " return std::nullopt;\n"; in runTargetDesc()
1790 OS << "}\n\n"; in runTargetDesc()
1792 OS << "const " << TargetName << "FrameLowering *\n" in runTargetDesc()
1799 OS << "} // end namespace llvm\n\n"; in runTargetDesc()
1800 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1803 void RegisterInfoEmitter::run(raw_ostream &OS) { in run() argument
1806 runEnums(OS, Target, RegBank); in run()
1809 runMCDesc(OS, Target, RegBank); in run()
1812 runTargetHeader(OS, Target, RegBank); in run()
1815 runTargetDesc(OS, Target, RegBank); in run()
1821 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { in debugDump() argument
1832 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1833 OS << "\tSpillSize: {"; in debugDump()
1835 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; in debugDump()
1836 OS << " }\n\tSpillAlignment: {"; in debugDump()
1838 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; in debugDump()
1839 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; in debugDump()
1840 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; in debugDump()
1841 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; in debugDump()
1842 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; in debugDump()
1843 OS << "\tAllocatable: " << RC.Allocatable << '\n'; in debugDump()
1844 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n'; in debugDump()
1845 OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n'; in debugDump()
1846 OS << "\tRegs:"; in debugDump()
1848 OS << " " << R->getName(); in debugDump()
1850 OS << '\n'; in debugDump()
1851 OS << "\tSubClasses:"; in debugDump()
1856 OS << " " << SRC.getName(); in debugDump()
1858 OS << '\n'; in debugDump()
1859 OS << "\tSuperClasses:"; in debugDump()
1861 OS << " " << SRC->getName(); in debugDump()
1863 OS << '\n'; in debugDump()
1867 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1868 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump()
1869 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; in debugDump()
1870 OS << "\tOffset: {"; in debugDump()
1872 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Offset; in debugDump()
1873 OS << " }\n\tSize: {"; in debugDump()
1875 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Size; in debugDump()
1876 OS << " }\n"; in debugDump()
1880 OS << "Register " << R.getName() << ":\n"; in debugDump()
1881 OS << "\tCostPerUse: "; in debugDump()
1883 OS << Cost << " "; in debugDump()
1884 OS << '\n'; in debugDump()
1885 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; in debugDump()
1886 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; in debugDump()
1889 OS << "\tSubReg " << P.first->getName() << " = " << P.second->getName() in debugDump()