Lines Matching +full:global +full:- +full:regs
1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
49 cl::OptionCategory RegisterInfoCat("Options for -gen-register-info");
52 RegisterInfoDebug("register-info-debug", cl::init(false),
68 // runEnums - Print out enum values for all of the registers.
71 // runMCDesc - Print out MC register descriptions.
74 // runTargetHeader - Emit a header fragment for the register info emitter.
78 // runTargetDesc - Output the target register and register file descriptions.
82 // run - Output the register file description.
88 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
91 const std::deque<CodeGenRegister> &Regs,
103 // runEnums - Print out enum values for all of the registers.
109 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); in runEnums()
111 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); in runEnums()
165 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
218 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
220 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
230 << " return RCWeightTable[RC->getID()];\n" in EmitRegUnitPressure()
318 PSetsSeqs.emit(OS, printInt, "-1"); in EmitRegUnitPressure()
323 << "/// Returns a -1 terminated array of pressure set IDs\n" in EmitRegUnitPressure()
326 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
332 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" in EmitRegUnitPressure()
337 << "/// Returns a -1 terminated array of pressure set IDs\n" in EmitRegUnitPressure()
342 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
358 // Sort and unique to get a map-like vector. We want the last assignment to in finalizeDwarfRegNumsKeys()
367 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) in finalizeDwarfRegNumsKeys()
368 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + in finalizeDwarfRegNumsKeys()
375 return A.first->getName() == B.first->getName(); in finalizeDwarfRegNumsKeys()
381 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
387 for (auto &RE : Regs) { in EmitRegMappingTables()
389 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); in EmitRegMappingTables()
398 // Now we know maximal length of number list. Append -1's, where needed in EmitRegMappingTables()
401 DwarfRegNum.second.push_back(-1); in EmitRegMappingTables()
403 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
405 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; in EmitRegMappingTables()
436 // We have to store the size in a const global, it's used in multiple in EmitRegMappingTables()
448 for (auto &RE : Regs) { in EmitRegMappingTables()
450 const RecordVal *V = Reg->getValue("DwarfAlias"); in EmitRegMappingTables()
451 if (!V || !V->getValue()) in EmitRegMappingTables()
454 DefInit *DI = cast<DefInit>(V->getValue()); in EmitRegMappingTables()
455 Record *Alias = DI->getDef(); in EmitRegMappingTables()
460 assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias && in EmitRegMappingTables()
466 assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg && in EmitRegMappingTables()
468 RegIter->second = AliasIter->second; in EmitRegMappingTables()
483 if (RegNo == -1) // -1 is the default value, don't emit a mapping. in EmitRegMappingTables()
494 // We have to store the size in a const global, it's used in multiple in EmitRegMappingTables()
508 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
512 for (auto &RE : Regs) { in EmitRegMapping()
515 Reg->getValueAsListOfInts("DwarfNumbers").size()); in EmitRegMapping()
521 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMapping()
538 OS << "RI->"; in EmitRegMapping()
569 OS << "RI->"; in EmitRegMapping()
586 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
619 OS << Idx->EnumValue; in printSubRegIndex()
642 V.push_back(Cur - Val); in diffEncode()
653 unsigned Cur = (*I)->EnumValue; in diffEncode()
654 V.push_back(Cur - Val); in diffEncode()
670 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); in combine()
672 CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; in combine()
679 auto *&Entry = Vec[I.first->EnumValue - 1]; in combine()
693 // Many sub-register indexes are composition-compatible, meaning that in emitComposeSubRegIndices()
697 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. in emitComposeSubRegIndices()
700 // Map each Sub-register index to a compatible table row. in emitComposeSubRegIndices()
739 OS << Rows[r][i]->getQualifiedName() << ", "; in emitComposeSubRegIndices()
746 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n" in emitComposeSubRegIndices()
747 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; in emitComposeSubRegIndices()
822 " --IdxA; assert(IdxA < " in emitComposeSubRegIndexLaneMask()
828 " Ops->Mask.any(); ++Ops) {\n" in emitComposeSubRegIndexLaneMask()
830 "Ops->Mask.getAsInteger();\n" in emitComposeSubRegIndexLaneMask()
831 " if (unsigned S = Ops->RotateLeft)\n" in emitComposeSubRegIndexLaneMask()
832 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - " in emitComposeSubRegIndexLaneMask()
844 " --IdxA; assert(IdxA < " in emitComposeSubRegIndexLaneMask()
850 " Ops->Mask.any(); ++Ops) {\n" in emitComposeSubRegIndexLaneMask()
852 " if (unsigned S = Ops->RotateLeft)\n" in emitComposeSubRegIndexLaneMask()
853 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - " in emitComposeSubRegIndexLaneMask()
863 // runMCDesc - Print out MC register descriptions.
872 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
875 // The lists of sub-registers and super-registers go in the same array. That in runMCDesc()
881 SmallVector<DiffVec, 4> SubRegLists(Regs.size()); in runMCDesc()
882 SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); in runMCDesc()
883 SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); in runMCDesc()
887 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); in runMCDesc()
889 // Keep track of sub-register names as well. These are not differentially in runMCDesc()
893 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); in runMCDesc()
899 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { in runMCDesc()
903 // Compute the ordered sub-register list. in runMCDesc()
909 // Compute the corresponding sub-register indexes. in runMCDesc()
915 // Super-registers are already computed. in runMCDesc()
952 // Emit the table of sub-register indexes. in runMCDesc()
968 for (const auto &Reg : Regs) { in runMCDesc()
974 assert(isUInt<32 - RegUnitBits>(Offset) && "Offset is too big"); in runMCDesc()
995 OS << LS << getQualifiedName(R->TheDef); in runMCDesc()
1016 // Emit the register list now (unless it would be a zero-length array). in runMCDesc()
1029 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); in runMCDesc()
1063 EmitRegMappingTables(OS, Regs, false); in runMCDesc()
1070 for (const auto &RE : Regs) { in runMCDesc()
1072 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); in runMCDesc()
1074 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { in runMCDesc()
1075 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) in runMCDesc()
1076 Value |= (uint64_t)B->getValue() << b; in runMCDesc()
1087 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " in runMCDesc()
1088 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " in runMCDesc()
1096 EmitRegMapping(OS, Regs, false); in runMCDesc()
1187 // runTargetDesc - Output the target register and register file descriptions.
1245 // Emit the table of sub-register index sizes. in runTargetDesc()
1249 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; in runTargetDesc()
1302 // register class, RC, is the set of sub-classes, including RC itself. in runTargetDesc()
1304 // If RC has super-registers, also create a list of subreg indices and bit in runTargetDesc()
1310 // The 0-terminated list of subreg indices starts at: in runTargetDesc()
1312 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... in runTargetDesc()
1314 // The corresponding bitmasks follow the sub-class mask in memory. Each in runTargetDesc()
1319 // Compress the sub-reg index lists. in runTargetDesc()
1330 // Emit super-reg class masks for any relevant SubRegIndices that can in runTargetDesc()
1352 // Emit NULL terminated super-class lists. in runTargetDesc()
1363 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1399 // Now emit the actual value-initialized register class instances. in runTargetDesc()
1440 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1442 for (const auto &Reg : Regs) in runTargetDesc()
1446 llvm::BitVector InAllocClass(Regs.size() + 1, false); in runTargetDesc()
1452 for (const auto &Reg : Regs) { in runTargetDesc()
1457 NumRegCosts - Costs.size(), 0); in runTargetDesc()
1463 // Emit the cost values as a 1D-array after grouping them by their indices, in runTargetDesc()
1465 // Size of the emitted array should be NumRegCosts * (Regs.size() + 1). in runTargetDesc()
1515 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1516 << " -> " << SRC->getName() << "\n"; in runTargetDesc()
1523 << " if (!Idx) return RC;\n --Idx;\n" in runTargetDesc()
1525 << " unsigned TV = Table[RC->getID()][Idx];\n" in runTargetDesc()
1526 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; in runTargetDesc()
1552 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second; in runTargetDesc()
1553 EnumValue = SubRegClass->EnumValue + 1; in runTargetDesc()
1560 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second; in runTargetDesc()
1561 OS << " -> " << SubRegClass->getName(); in runTargetDesc()
1570 << " if (!Idx) return RC;\n --Idx;\n" in runTargetDesc()
1572 << " unsigned TV = Table[RC->getID()][Idx];\n" in runTargetDesc()
1573 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; in runTargetDesc()
1594 return std::pair(*LHS->getBaseClassOrder(), LHS->EnumValue) < in runTargetDesc()
1595 std::pair(*RHS->getBaseClassOrder(), RHS->EnumValue); in runTargetDesc()
1606 OS << " static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n"; in runTargetDesc()
1608 for (const CodeGenRegister &Reg : Regs) { in runTargetDesc()
1611 if (is_contained(RC->getMembers(), &Reg)) { in runTargetDesc()
1618 << (BaseRC ? BaseRC->getQualifiedIdName() : "InvalidRegClassID") in runTargetDesc()
1641 EmitRegMappingTables(OS, Regs, true); in runTargetDesc()
1654 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 in runTargetDesc()
1667 EmitRegMapping(OS, Regs, true); in runTargetDesc()
1676 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
1677 assert(Regs && "Cannot expand CalleeSavedRegs instance"); in runTargetDesc()
1679 // Emit the *_SaveList list of callee-saved registers. in runTargetDesc()
1680 OS << "static const MCPhysReg " << CSRSet->getName() << "_SaveList[] = { "; in runTargetDesc()
1681 for (unsigned r = 0, re = Regs->size(); r != re; ++r) in runTargetDesc()
1682 OS << getQualifiedName((*Regs)[r]) << ", "; in runTargetDesc()
1685 // Emit the *_RegMask bit mask of call-preserved registers. in runTargetDesc()
1686 BitVector Covered = RegBank.computeCoveredRegisters(*Regs); in runTargetDesc()
1691 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { in runTargetDesc()
1693 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); in runTargetDesc()
1707 OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { "; in runTargetDesc()
1718 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1735 OS << " " << RC->getQualifiedName() in runTargetDesc()
1749 OS << " " << RC->getQualifiedName() in runTargetDesc()
1763 OS << " " << RC->getQualifiedName() in runTargetDesc()
1773 for (const auto &Reg : Regs) in runTargetDesc()
1784 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1825 auto getModeName = [CGH](unsigned M) -> StringRef { in debugDump()
1848 OS << " " << R->getName(); in debugDump()
1861 OS << " " << SRC->getName(); in debugDump()
1889 OS << "\tSubReg " << P.first->getName() << " = " << P.second->getName() in debugDump()
1896 X("gen-register-info", "Generate registers and register classes info");