1 //===- RISCVTargetDefEmitter.cpp - Generate lists of RISC-V CPUs ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // and RISCVISAInfo.cpp to parse the RISC-V CPUs and extensions.
12 //===----------------------------------------------------------------------===//
22   StringRef Name = R->getValueAsString("Name");  in getExtensionName()
23   Name.consume_front("experimental-");  in getExtensionName()
36     if (R->getValueAsBit("Experimental") != Experimental)  in printExtensionTable()
40        << R->getValueAsInt("MajorVersion") << ", "  in printExtensionTable()
41        << R->getValueAsInt("MinorVersion") << "}},\n";  in printExtensionTable()
69     for (Record *Ext : Extensions) {  in emitRISCVExtensions()
70       auto ImpliesList = Ext->getValueAsListOfDefs("Implies");  in emitRISCVExtensions()
74       StringRef Name = getExtensionName(Ext);  in emitRISCVExtensions()
77         if (!ImpliedExt->isSubClassOf("RISCVExtension"))  in emitRISCVExtensions()
92 // in RISC-V ISA specification (version 20191213) 'Chapter 27. ISA Extension
104     if (Feature->isSubClassOf("RISCVExtension")) {  in printMArch()
105       unsigned Major = Feature->getValueAsInt("MajorVersion");  in printMArch()
106       unsigned Minor = Feature->getValueAsInt("MinorVersion");  in printMArch()
122   for (auto const &Ext : Extensions)  in printMArch()  local
123     OS << LS << Ext.first << Ext.second.Major << 'p' << Ext.second.Minor;  in printMArch()
135     if (Rec->getValueAsBit("Experimental") != Experimental)  in printProfileTable()
138     StringRef Name = Rec->getValueAsString("Name");  in printProfileTable()
139     Name.consume_front("experimental-");  in printProfileTable()
141     printMArch(OS, Rec->getValueAsListOfDefs("Implies"));  in printProfileTable()
157       return Rec->getValueAsBit("Experimental");  in emitRISCVProfiles()
176         Rec->getValueAsListOfDefs("Features");  in emitRISCVProcs()
178       return Feature->getValueAsString("Name") == "unaligned-scalar-mem";  in emitRISCVProcs()
182       return Feature->getValueAsString("Name") == "unaligned-vector-mem";  in emitRISCVProcs()
185     OS << "PROC(" << Rec->getName() << ", {\"" << Rec->getValueAsString("Name")  in emitRISCVProcs()
188     StringRef MArch = Rec->getValueAsString("DefaultMarch");  in emitRISCVProcs()
206     OS << "TUNE_PROC(" << Rec->getName() << ", "  in emitRISCVProcs()
207        << "\"" << Rec->getValueAsString("Name") << "\")\n";  in emitRISCVProcs()
228     unsigned GroupIDVal = Rec->getValueAsInt("GroupID");  in emitRISCVExtensionBitmask()
229     unsigned BitPosVal = Rec->getValueAsInt("BitPos");  in emitRISCVExtensionBitmask()
231     StringRef ExtName = Rec->getValueAsString("Name");  in emitRISCVExtensionBitmask()
232     ExtName.consume_front("experimental-");  in emitRISCVExtensionBitmask()
255 static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,
257                                 "RISC-V");