Lines Matching full:extensions
10 // and RISCVISAInfo.cpp to parse the RISC-V CPUs and extensions.
28 const std::vector<Record *> &Extensions, in printExtensionTable() argument
33 OS << "Extensions[] = {\n"; in printExtensionTable()
35 for (Record *R : Extensions) { in printExtensionTable()
51 std::vector<Record *> Extensions = in emitRISCVExtensions() local
53 llvm::sort(Extensions, [](const Record *Rec1, const Record *Rec2) { in emitRISCVExtensions()
57 if (!Extensions.empty()) { in emitRISCVExtensions()
58 printExtensionTable(OS, Extensions, /*Experimental=*/false); in emitRISCVExtensions()
59 printExtensionTable(OS, Extensions, /*Experimental=*/true); in emitRISCVExtensions()
67 if (!Extensions.empty()) { in emitRISCVExtensions()
69 for (Record *Ext : Extensions) { in emitRISCVExtensions()
98 RISCVISAUtils::OrderedExtensionMap Extensions; in printMArch() local
107 Extensions[FeatureName.str()] = {Major, Minor}; in printMArch()
122 for (auto const &Ext : Extensions) in printMArch()
215 std::vector<Record *> Extensions = in emitRISCVExtensionBitmask() local
217 llvm::sort(Extensions, [](const Record *Rec1, const Record *Rec2) { in emitRISCVExtensionBitmask()
227 for (const Record *Rec : Extensions) { in emitRISCVExtensionBitmask()
256 "Generate the list of CPUs and extensions for "