Lines Matching refs:TheDef
138 StringRef InstName = Inst->TheDef->getName(); in apply()
141 Elts.insert(Inst->TheDef); in apply()
151 return LHS->TheDef->getName() < RHS; in apply()
154 return LHS < RHS->TheDef->getName() && in apply()
155 !RHS->TheDef->getName().starts_with(LHS); in apply()
166 StringRef InstName = Inst->TheDef->getName(); in apply()
168 Elts.insert(Inst->TheDef); in apply()
619 Record *SchedDef = Inst->TheDef; in collectSchedRW()
694 findRWs(CGRW.TheDef->getValueAsListOfDefs("Writes"), CGRW.Sequence, in collectSchedRW()
745 RWVec, [Def](const CodeGenSchedRW &RW) { return RW.TheDef == Def; }); in getSchedRWIdx()
788 int Repeat = SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1; in expandRWSequence()
812 PrintFatalError(AliasRW.TheDef->getLoc(), in expandRWSeqForProc()
817 AliasDef = AliasRW.TheDef; in expandRWSeqForProc()
829 SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1; in expandRWSeqForProc()
880 Record *ItinDef = Inst->TheDef->getValueAsDef("Itinerary"); in collectSchedClasses()
882 if (!Inst->TheDef->isValueUnset("SchedRW")) in collectSchedClasses()
883 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); in collectSchedClasses()
887 InstrClassMap[Inst->TheDef] = SCIdx; in collectSchedClasses()
907 StringRef InstName = Inst->TheDef->getName(); in collectSchedClasses()
912 dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n'; in collectSchedClasses()
918 PrintFatalError(Inst->TheDef->getLoc(), in collectSchedClasses()
962 dbgs() << "No machine model for " << Inst->TheDef->getName() in collectSchedClasses()
973 return InstrClassMap.lookup(Inst.TheDef); in getSchedClassIdx()
1376 RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants"); in mutuallyExclusive()
1436 if (SchedRW.TheDef->getValueInit("SchedModel")->isComplete()) { in getIntersectingVariants()
1437 Record *ModelDef = SchedRW.TheDef->getValueAsDef("SchedModel"); in getIntersectingVariants()
1442 const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants"); in getIntersectingVariants()
1474 const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants"); in getIntersectingVariants()
1479 Variants.emplace_back(AliasRW.TheDef, SchedRW.Index, AliasProcIdx, 0); in getIntersectingVariants()
1506 PrintFatalError(SchedRW.TheDef->getLoc(), in getIntersectingVariants()
1990 if (Inst->TheDef->isValueUnset("SchedRW")) { in checkCompleteness()
1991 PrintError(Inst->TheDef->getLoc(), in checkCompleteness()
1993 Inst->TheDef->getName() + "' in SchedMachineModel '" + in checkCompleteness()
2012 PrintError(Inst->TheDef->getLoc(), "'" + ProcModel.ModelName + in checkCompleteness()
2014 Inst->TheDef->getName() + "'"); in checkCompleteness()
2062 if (SchedRW.TheDef) { in collectRWResources()
2063 if (!IsRead && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) { in collectRWResources()
2065 addWriteRes(SchedRW.TheDef, Idx); in collectRWResources()
2066 } else if (IsRead && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) { in collectRWResources()
2068 addReadAdvance(SchedRW.TheDef, Idx); in collectRWResources()
2207 for (const Record *TheDef : UnsupportedFeaturesDefs) { in isUnsupported() local
2209 Inst.TheDef->getValueAsListOfDefs("Predicates")) { in isUnsupported()
2210 if (TheDef->getName() == PredDef->getName()) in isUnsupported()