Lines Matching refs:RC
1011 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
1012 RC.SubClasses.resize(RegClasses.size()); in computeSubClasses()
1013 RC.SubClasses.set(RC.EnumValue); in computeSubClasses()
1014 if (RC.Artificial) in computeSubClasses()
1020 if (RC.SubClasses.test(SubRC.EnumValue)) in computeSubClasses()
1022 if (!testSubClass(&RC, &SubRC)) in computeSubClasses()
1026 RC.SubClasses |= SubRC.SubClasses; in computeSubClasses()
1030 for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2) in computeSubClasses()
1031 RC.SubClasses.set(I2->EnumValue); in computeSubClasses()
1035 for (auto &RC : RegClasses) { in computeSubClasses() local
1036 const BitVector &SC = RC.getSubClasses(); in computeSubClasses()
1042 if (&*I == &RC) in computeSubClasses()
1044 I->SuperClasses.push_back(&RC); in computeSubClasses()
1051 for (auto &RC : RegClasses) in computeSubClasses() local
1052 if (!RC.getDef()) in computeSubClasses()
1053 RC.inheritProperties(RegBank); in computeSubClasses()
1079 for (auto &RC : RegClasses) in getMatchingSubClassWithSubRegs() local
1080 if (SuperRegRCsBV[RC.EnumValue]) in getMatchingSubClassWithSubRegs()
1081 SuperRegRCs.emplace_back(&RC); in getMatchingSubClassWithSubRegs()
1089 for (auto &RC : RegClasses) { in getMatchingSubClassWithSubRegs() local
1091 RC.getSuperRegClasses(SubIdx, SuperRegClassesBV); in getMatchingSubClassWithSubRegs()
1093 SuperRegClasses.push_back(std::pair(&RC, SuperRegClassesBV)); in getMatchingSubClassWithSubRegs()
1147 for (CodeGenRegisterClass *RC : FindI->second) in getSuperRegClasses()
1148 Out.set(RC->EnumValue); in getSuperRegClasses()
1232 for (Record *RC : TupRegs) in CodeGenRegBank()
1233 getReg(RC); in CodeGenRegBank()
1301 CodeGenRegisterClass &RC = RegClasses.back(); in CodeGenRegBank() local
1302 if (!RC.Artificial) in CodeGenRegBank()
1303 addToMaps(&RC); in CodeGenRegBank()
1312 for (auto &RC : RegClasses) in CodeGenRegBank() local
1313 RC.EnumValue = i++; in CodeGenRegBank()
1353 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) { in addToMaps() argument
1354 if (Record *Def = RC->getDef()) in addToMaps()
1355 Def2RC.insert(std::pair(Def, RC)); in addToMaps()
1359 CodeGenRegisterClass::Key K(*RC); in addToMaps()
1360 Key2RC.insert(std::pair(K, RC)); in addToMaps()
1365 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, in getOrCreateSubClass() argument
1369 CodeGenRegisterClass::Key K(Members, RC->RSI); in getOrCreateSubClass()
1381 if (CodeGenRegisterClass *RC = Def2RC.lookup(Def)) in getRegClass() local
1382 return RC; in getRegClass()
2016 for (auto &RC : RegClasses) { in computeRegUnitSets() local
2017 if (!RC.Allocatable || RC.Artificial || !RC.GeneratePressureSet) in computeRegUnitSets()
2021 RegUnitSet RUSet(RC.getName()); in computeRegUnitSets()
2022 RC.buildRegUnitSet(*this, RUSet.Units); in computeRegUnitSets()
2107 for (auto &RC : RegClasses) { in computeRegUnitSets() local
2109 if (!RC.Allocatable) in computeRegUnitSets()
2114 RC.buildRegUnitSet(*this, RCRegUnits); in computeRegUnitSets()
2120 LLVM_DEBUG(dbgs() << "RC " << RC.getName() << " Units:\n"; in computeRegUnitSets()
2134 assert((!RegClassUnitSets[RCIdx].empty() || !RC.GeneratePressureSet) && in computeRegUnitSets()
2217 for (CodeGenRegisterClass &RC : RegClasses) { in computeDerivedInfo()
2218 RC.HasDisjunctSubRegs = false; in computeDerivedInfo()
2219 RC.CoveredBySubRegs = true; in computeDerivedInfo()
2220 for (const CodeGenRegister *Reg : RC.getMembers()) { in computeDerivedInfo()
2221 RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs; in computeDerivedInfo()
2222 RC.CoveredBySubRegs &= Reg->CoveredBySubRegs; in computeDerivedInfo()
2250 void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) { in inferCommonSubClass() argument
2256 CodeGenRegisterClass *RC1 = RC; in inferCommonSubClass()
2290 void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) { in inferSubClassWithSubReg() argument
2298 for (const auto R : RC->getMembers()) { in inferSubClassWithSubReg()
2321 if (I->second.size() == RC->getMembers().size()) { in inferSubClassWithSubReg()
2322 RC->setSubClassWithSubReg(&SubIdx, RC); in inferSubClassWithSubReg()
2327 RC, &I->second, RC->getName() + "_with_" + I->first->getName()); in inferSubClassWithSubReg()
2328 RC->setSubClassWithSubReg(&SubIdx, SubRC); in inferSubClassWithSubReg()
2340 CodeGenRegisterClass *RC, in inferMatchingSuperRegClass() argument
2351 if (RC->getSubClassWithSubReg(&SubIdx) != RC) in inferMatchingSuperRegClass()
2357 for (const auto Super : RC->getMembers()) { in inferMatchingSuperRegClass()
2392 if (SubSetVec.size() == RC->getMembers().size()) { in inferMatchingSuperRegClass()
2393 SubRC.addSuperRegClass(&SubIdx, RC); in inferMatchingSuperRegClass()
2399 getOrCreateSubClass(RC, &SubSetVec, in inferMatchingSuperRegClass()
2400 RC->getName() + "_with_" + SubIdx.getName() + "_in_" + in inferMatchingSuperRegClass()
2422 CodeGenRegisterClass *RC = &*I; in computeInferredRegisterClasses() local
2423 if (RC->Artificial) in computeInferredRegisterClasses()
2427 inferSubClassWithSubReg(RC); in computeInferredRegisterClasses()
2430 inferCommonSubClass(RC); in computeInferredRegisterClasses()
2433 inferMatchingSuperRegClass(RC); in computeInferredRegisterClasses()
2459 for (const auto &RC : getRegClasses()) { in getRegClassForRegister() local
2460 if (!RC.contains(Reg)) in getRegClassForRegister()
2466 FoundRC = &RC; in getRegClassForRegister()
2471 if (RC.getValueTypes() != FoundRC->getValueTypes()) in getRegClassForRegister()
2477 if (RC.hasSubClass(FoundRC)) { in getRegClassForRegister()
2478 FoundRC = &RC; in getRegClassForRegister()
2485 if (FoundRC->hasSubClass(&RC)) in getRegClassForRegister()
2500 for (const auto &RC : getRegClasses()) { in getMinimalPhysRegClass() local
2501 if ((!VT || RC.hasType(*VT)) && RC.contains(Reg) && in getMinimalPhysRegClass()
2502 (!BestRC || BestRC->hasSubClass(&RC))) in getMinimalPhysRegClass()
2503 BestRC = &RC; in getMinimalPhysRegClass()