Lines Matching +full:super +full:- +full:set
1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
37 #include <set>
45 #define DEBUG_TYPE "regalloc-emitter"
47 //===----------------------------------------------------------------------===//
49 //===----------------------------------------------------------------------===//
54 Name = std::string(R->getName()); in CodeGenSubRegIndex()
55 if (R->getValue("Namespace")) in CodeGenSubRegIndex()
56 Namespace = std::string(R->getValueAsString("Namespace")); in CodeGenSubRegIndex()
58 if (const RecordVal *RV = R->getValue("SubRegRanges")) in CodeGenSubRegIndex()
59 if (auto *DI = dyn_cast_or_null<DefInit>(RV->getValue())) in CodeGenSubRegIndex()
60 Range = SubRegRangeByHwMode(DI->getDef(), CGH); in CodeGenSubRegIndex()
68 Range(SubRegRange(-1, -1)), EnumValue(Enum), AllSuperRegsCovered(true), in CodeGenSubRegIndex()
83 std::vector<Record *> Comps = TheDef->getValueAsListOfDefs("ComposedOf"); in updateComponents()
86 PrintFatalError(TheDef->getLoc(), in updateComponents()
90 CodeGenSubRegIndex *X = A->addComposite(B, this, RegBank.getHwModes()); in updateComponents()
92 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries"); in updateComponents()
96 TheDef->getValueAsListOfDefs("CoveringSubRegIndices"); in updateComponents()
99 PrintFatalError(TheDef->getLoc(), in updateComponents()
116 // The lane mask is simply the union of all sub-indices. in computeLaneMask()
119 M |= C.second->computeLaneMask(); in computeLaneMask()
120 assert(M.any() && "Missing lane mask, sub-register cycle?"); in computeLaneMask()
140 SubIdx->computeConcatTransitiveClosure(); in computeConcatTransitiveClosure()
142 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) in computeConcatTransitiveClosure()
143 assert(SRI->ConcatenationOf.empty() && "No transitive closure?"); in computeConcatTransitiveClosure()
146 if (SubIdx->ConcatenationOf.empty()) { in computeConcatTransitiveClosure()
150 I = ConcatenationOf.insert(I, SubIdx->ConcatenationOf.begin(), in computeConcatTransitiveClosure()
151 SubIdx->ConcatenationOf.end()); in computeConcatTransitiveClosure()
152 I += SubIdx->ConcatenationOf.size(); in computeConcatTransitiveClosure()
157 //===----------------------------------------------------------------------===//
159 //===----------------------------------------------------------------------===//
163 CostPerUse(R->getValueAsListOfInts("CostPerUse")), in CodeGenRegister()
164 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")), in CodeGenRegister()
165 HasDisjunctSubRegs(false), Constant(R->getValueAsBit("isConstant")), in CodeGenRegister()
167 Artificial = R->getValueAsBit("isArtificial"); in CodeGenRegister()
171 std::vector<Record *> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices"); in buildObjectGraph()
172 std::vector<Record *> SRs = TheDef->getValueAsListOfDefs("SubRegs"); in buildObjectGraph()
175 PrintFatalError(TheDef->getLoc(), in buildObjectGraph()
183 // Also compute leading super-registers. Each register has a list of in buildObjectGraph()
184 // covered-by-subregs super-registers where it appears as the first explicit in buildObjectGraph()
185 // sub-register. in buildObjectGraph()
189 ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this); in buildObjectGraph()
193 std::vector<Record *> Aliases = TheDef->getValueAsListOfDefs("Aliases"); in buildObjectGraph()
197 Reg->ExplicitAliases.push_back(this); in buildObjectGraph()
203 return TheDef->getName(); in getName()
208 // Iterate over all register units in a set of registers.
222 UnitI = (*RegI)->getRegUnits().begin(); in RegUnitIterator()
223 UnitE = (*RegI)->getRegUnits().end(); in RegUnitIterator()
252 UnitI = (*RegI)->getRegUnits().begin(); in advance()
253 UnitE = (*RegI)->getRegUnits().end(); in advance()
269 changed |= (RegUnits |= SR->RegUnits); in inheritRegUnits()
288 if (!SR->Artificial) in computeSubRegs()
289 Idx->Artificial = false; in computeSubRegs()
291 PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() + in computeSubRegs()
294 // Map explicit sub-registers first, so the names take precedence. in computeSubRegs()
295 // The inherited sub-registers are mapped below. in computeSubRegs()
303 // Here the order is important - earlier subregs take precedence. in computeSubRegs()
305 const SubRegMap &Map = ESR->computeSubRegs(RegBank); in computeSubRegs()
306 HasDisjunctSubRegs |= ESR->HasDisjunctSubRegs; in computeSubRegs()
321 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites(); in computeSubRegs()
323 const SubRegMap &Map = SR->computeSubRegs(RegBank); in computeSubRegs()
330 continue; // Idx + I->first doesn't exist in SR. in computeSubRegs()
331 // Add I->second as a name for the subreg SRI->second, assuming it is in computeSubRegs()
333 if (SubRegs.count(Comp.second) || !Orphans.erase(SRI->second)) in computeSubRegs()
335 // We found a new name for the orphaned sub-register. in computeSubRegs()
336 SubRegs.insert(std::pair(Comp.second, SRI->second)); in computeSubRegs()
343 // Work backwards in the Indices vector in order to compose subregs bottom-up. in computeSubRegs()
346 // qsub_1 -> dsub_0 -> ssub_0 in computeSubRegs()
348 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register in computeSubRegs()
351 // qsub_1 -> ssub_0 in computeSubRegs()
352 // dsub_2 -> ssub_0 in computeSubRegs()
356 // dsub_2 -> ssub_0 composition can be shared. in computeSubRegs()
360 const SubRegMap &Map = SR->computeSubRegs(RegBank); in computeSubRegs()
367 // Compute the inverse SubReg -> Idx map. in computeSubRegs()
372 Loc = TheDef->getLoc(); in computeSubRegs()
374 " has itself as a sub-register"); in computeSubRegs()
379 SubReg.first->AllSuperRegsCovered = false; in computeSubRegs()
381 // Ensure that every sub-register has a unique name. in computeSubRegs()
384 if (Ins->second == SubReg.first) in computeSubRegs()
389 Loc = TheDef->getLoc(); in computeSubRegs()
391 Loc, "Sub-register can't have two names: " + SubReg.second->getName() + in computeSubRegs()
392 " available as " + SubReg.first->getName() + " and " + in computeSubRegs()
393 Ins->second->getName()); in computeSubRegs()
396 // Derive possible names for sub-register concatenations from any explicit in computeSubRegs()
397 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure in computeSubRegs()
402 if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1 || in computeSubRegs()
403 SR->Artificial) in computeSubRegs()
406 // SR is composed of multiple sub-regs. Find their names in this register. in computeSubRegs()
408 for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j) { in computeSubRegs()
409 CodeGenSubRegIndex &I = *SR->ExplicitSubRegIndices[j]; in computeSubRegs()
411 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j])); in computeSubRegs()
422 // Inherit all sub-register units. It is good enough to look at the explicit in computeSubRegs()
423 // sub-registers, the other registers won't contribute any more units. in computeSubRegs()
426 RegUnits |= SR->RegUnits; in computeSubRegs()
441 if (AR->SubRegsComplete) in computeSubRegs()
446 RegUnits.set(Unit); in computeSubRegs()
447 AR->RegUnits.set(Unit); in computeSubRegs()
451 // a leaf register with ad hoc aliases doesn't get its own unit - it isn't in computeSubRegs()
454 RegUnits.set(RegBank.newRegUnit(this)); in computeSubRegs()
463 // In a register that is covered by its sub-registers, try to find redundant
464 // sub-registers. For example:
470 // We can infer that D1_D2 is also a sub-register, even if it wasn't named in
474 // sub-register relationships that would force a DAG.
483 // Look at the leading super-registers of each sub-register. Those are the in computeSecondarySubRegs()
484 // candidates for new sub-registers, assuming they are fully contained in in computeSecondarySubRegs()
492 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs; in computeSecondarySubRegs()
495 // Already got this sub-register? in computeSecondarySubRegs()
498 // Check if each component of Cand is already a sub-register. in computeSecondarySubRegs()
499 assert(!Cand->ExplicitSubRegs.empty() && in computeSecondarySubRegs()
500 "Super-register has no sub-registers"); in computeSecondarySubRegs()
501 if (Cand->ExplicitSubRegs.size() == 1) in computeSecondarySubRegs()
506 assert(Cand->ExplicitSubRegs[0] == SubReg && "LeadingSuperRegs correct"); in computeSecondarySubRegs()
508 for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) { in computeSecondarySubRegs()
510 if (SubRegIdx->ConcatenationOf.empty()) in computeSecondarySubRegs()
513 append_range(Parts, SubRegIdx->ConcatenationOf); in computeSecondarySubRegs()
515 // Sub-register doesn't exist. in computeSecondarySubRegs()
520 // There is nothing to do if some Cand sub-register is not part of this in computeSecondarySubRegs()
525 // Each part of Cand is a sub-register of this. Make the full Cand also in computeSecondarySubRegs()
526 // a sub-register with a concatenated sub-register index. in computeSecondarySubRegs()
542 // Create sub-register index composition maps for the synthesized indices. in computeSecondarySubRegs()
546 for (auto SubReg : NewSubReg->SubRegs) { in computeSecondarySubRegs()
549 PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " + in computeSecondarySubRegs()
550 SubReg.second->getName() + in computeSecondarySubRegs()
552 NewIdx->addComposite(SubReg.first, SubIdx, RegBank.getHwModes()); in computeSecondarySubRegs()
563 // Make sure all sub-registers have been visited first, so the super-reg in computeSuperRegs()
566 SubReg.second->computeSuperRegs(RegBank); in computeSuperRegs()
568 // Now add this as a super-register on all sub-registers. in computeSuperRegs()
569 // Also compute the TopoSigId in post-order. in computeSuperRegs()
574 Id.push_back(SubReg.first->EnumValue); in computeSuperRegs()
575 Id.push_back(SubReg.second->TopoSig); in computeSuperRegs()
578 if (!SubReg.second->SuperRegs.empty() && in computeSuperRegs()
579 SubReg.second->SuperRegs.back() == this) in computeSuperRegs()
581 SubReg.second->SuperRegs.push_back(this); in computeSuperRegs()
588 assert(SubRegsComplete && "Must precompute sub-registers"); in addSubRegsPreOrder()
592 SR->addSubRegsPreOrder(OSet, RegBank); in addSubRegsPreOrder()
594 // Add any secondary sub-registers that weren't part of the explicit tree. in addSubRegsPreOrder()
608 //===----------------------------------------------------------------------===//
610 //===----------------------------------------------------------------------===//
612 // A RegisterTuples def is used to generate pseudo-registers from lists of
613 // sub-registers. We provide a SetTheory expander class that returns the new
629 std::vector<Record *> Indices = Def->getValueAsListOfDefs("SubRegIndices"); in expand()
631 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); in expand()
632 if (Dim != SubRegs->size()) in expand()
633 PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch"); in expand()
635 PrintFatalError(Def->getLoc(), in expand()
636 "Tuples must have at least 2 sub-registers"); in expand()
638 // Evaluate the sub-register lists to be zipped. in expand()
642 ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc()); in expand()
650 Record *RegisterCl = Def->getRecords().getClass("Register"); in expand()
653 Def->getValueAsListOfStrings("RegAsmNames"); in expand()
656 RecordKeeper &RK = Def->getRecords(); in expand()
665 Name += Reg->getName(); in expand()
670 ListInit *CostList = Proto->getValueAsListInit("CostPerUse"); in expand()
672 CostPerUse.insert(CostPerUse.end(), CostList->begin(), CostList->end()); in expand()
677 PrintFatalError(Def->getLoc(), in expand()
687 std::make_unique<Record>(Name, Def->getLoc(), Def->getRecords())); in expand()
692 const auto Res = TupleNames.insert(NewReg->getName()); in expand()
694 PrintFatalError(Def->getLoc(), in expand()
697 // Copy Proto super-classes. in expand()
698 ArrayRef<std::pair<Record *, SMRange>> Supers = Proto->getSuperClasses(); in expand()
700 NewReg->addSuperClass(SuperPair.first, SuperPair.second); in expand()
703 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) { in expand()
704 RecordVal RV = Proto->getValues()[i]; in expand()
707 if (NewReg->getValue(RV.getNameInit())) in expand()
712 // Replace the sub-register list with Tuple. in expand()
721 RV.setValue(ListInit::get(CostPerUse, CostList->getElementType())); in expand()
723 // Composite registers are always covered by sub-registers. in expand()
729 NewReg->addValue(*Def->getValue(Field)); in expand()
736 if (const RecordVal *DefRV = RegisterCl->getValue(Field)) in expand()
737 NewReg->addValue(*DefRV); in expand()
742 NewReg->addValue(RV); in expand()
750 //===----------------------------------------------------------------------===//
752 //===----------------------------------------------------------------------===//
760 : TheDef(R), Name(std::string(R->getName())), in CodeGenRegisterClass()
761 TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), TSFlags(0) { in CodeGenRegisterClass()
762 GeneratePressureSet = R->getValueAsBit("GeneratePressureSet"); in CodeGenRegisterClass()
763 std::vector<Record *> TypeList = R->getValueAsListOfDefs("RegTypes"); in CodeGenRegisterClass()
765 PrintFatalError(R->getLoc(), "RegTypes list must not be empty!"); in CodeGenRegisterClass()
768 if (!Type->isSubClassOf("ValueType")) in CodeGenRegisterClass()
769 PrintFatalError(R->getLoc(), in CodeGenRegisterClass()
770 "RegTypes list member '" + Type->getName() + in CodeGenRegisterClass()
775 // Allocation order 0 is the full set. AltOrders provides others. in CodeGenRegisterClass()
777 ListInit *AltOrders = R->getValueAsListInit("AltOrders"); in CodeGenRegisterClass()
778 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
782 for (unsigned i = 0, e = Elements->size(); i != e; ++i) { in CodeGenRegisterClass()
786 Artificial &= Reg->Artificial; in CodeGenRegisterClass()
787 TopoSigs.set(Reg->getTopoSig()); in CodeGenRegisterClass()
793 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { in CodeGenRegisterClass()
794 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); in CodeGenRegisterClass()
801 PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() + in CodeGenRegisterClass()
806 Namespace = R->getValueAsString("Namespace"); in CodeGenRegisterClass()
808 if (const RecordVal *RV = R->getValue("RegInfos")) in CodeGenRegisterClass()
809 if (DefInit *DI = dyn_cast_or_null<DefInit>(RV->getValue())) in CodeGenRegisterClass()
810 RSI = RegSizeInfoByHwMode(DI->getDef(), RegBank.getHwModes()); in CodeGenRegisterClass()
811 unsigned Size = R->getValueAsInt("Size"); in CodeGenRegisterClass()
818 RI.SpillAlignment = R->getValueAsInt("Alignment"); in CodeGenRegisterClass()
822 CopyCost = R->getValueAsInt("CopyCost"); in CodeGenRegisterClass()
823 Allocatable = R->getValueAsBit("isAllocatable"); in CodeGenRegisterClass()
824 AltOrderSelect = R->getValueAsString("AltOrderSelect"); in CodeGenRegisterClass()
825 int AllocationPriority = R->getValueAsInt("AllocationPriority"); in CodeGenRegisterClass()
827 PrintFatalError(R->getLoc(), "AllocationPriority out of range [0,31]"); in CodeGenRegisterClass()
828 this->AllocationPriority = AllocationPriority; in CodeGenRegisterClass()
830 GlobalPriority = R->getValueAsBit("GlobalPriority"); in CodeGenRegisterClass()
832 BitsInit *TSF = R->getValueAsBitsInit("TSFlags"); in CodeGenRegisterClass()
833 for (unsigned I = 0, E = TSF->getNumBits(); I != E; ++I) { in CodeGenRegisterClass()
834 BitInit *Bit = cast<BitInit>(TSF->getBit(I)); in CodeGenRegisterClass()
835 TSFlags |= uint8_t(Bit->getValue()) << I; in CodeGenRegisterClass()
840 // Most properties will be inherited from the closest super-class after the
845 TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), RSI(Props.RSI), in CodeGenRegisterClass()
851 TopoSigs.set(R->getTopoSig()); in CodeGenRegisterClass()
852 Artificial &= R->Artificial; in CodeGenRegisterClass()
859 assert(!SuperClasses.empty() && "Synthesized class without super class"); in inheritProperties()
861 // The last super-class is the smallest one. in inheritProperties()
862 CodeGenRegisterClass &Super = *SuperClasses.back(); in inheritProperties() local
866 Namespace = Super.Namespace; in inheritProperties()
867 VTs = Super.VTs; in inheritProperties()
868 CopyCost = Super.CopyCost; in inheritProperties()
871 return S->Allocatable; in inheritProperties()
873 AltOrderSelect = Super.AltOrderSelect; in inheritProperties()
874 AllocationPriority = Super.AllocationPriority; in inheritProperties()
875 GlobalPriority = Super.GlobalPriority; in inheritProperties()
876 TSFlags = Super.TSFlags; in inheritProperties()
877 GeneratePressureSet |= Super.GeneratePressureSet; in inheritProperties()
880 // super-class. in inheritProperties()
881 Orders.resize(Super.Orders.size()); in inheritProperties()
882 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) in inheritProperties()
883 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) in inheritProperties()
884 if (contains(RegBank.getReg(Super.Orders[i][j]))) in inheritProperties()
885 Orders[i].push_back(Super.Orders[i][j]); in inheritProperties()
895 // The motivating example came from RISC-V, where (likely because of being in hasType()
896 // guarded by "64-bit" predicate), the type of X5 was {*:[i64]}, but the in hasType()
914 if (TheDef && !TheDef->isValueUnset("Weight")) in getWeight()
915 return TheDef->getValueAsInt("Weight"); in getWeight()
920 return (*Members.begin())->getWeight(RegBank); in getWeight()
928 OS << ", " << R->getName(); in operator <<()
943 // RC is a sub-class of this class if it is a valid replacement for any
953 return A->RSI.isSubClassOf(B->RSI) && in testSubClass()
954 std::includes(A->getMembers().begin(), A->getMembers().end(), in testSubClass()
955 B->getMembers().begin(), B->getMembers().end(), in testSubClass()
960 /// ordering that arranges all register classes before their sub-classes.
972 if (A->RSI < B->RSI) in TopoOrderRC()
974 if (A->RSI != B->RSI) in TopoOrderRC()
977 // Order by descending set size. Note that the classes' allocation order may in TopoOrderRC()
978 // not have been computed yet. The Members set is always vaild. in TopoOrderRC()
979 if (A->getMembers().size() > B->getMembers().size()) in TopoOrderRC()
981 if (A->getMembers().size() < B->getMembers().size()) in TopoOrderRC()
985 return StringRef(A->getName()) < B->getName(); in TopoOrderRC()
1004 // Compute sub-classes of all register classes.
1009 // Visit backwards so sub-classes are seen first. in computeSubClasses()
1013 RC.SubClasses.set(RC.EnumValue); in computeSubClasses()
1024 // SubRC is a sub-class. Grap all its sub-classes so we won't have to in computeSubClasses()
1031 RC.SubClasses.set(I2->EnumValue); in computeSubClasses()
1038 for (int s = 0, next_s = SC.find_first(); next_s != -1; in computeSubClasses()
1040 std::advance(I, next_s - s); in computeSubClasses()
1044 I->SuperClasses.push_back(&RC); in computeSubClasses()
1049 // properties from their closest super-class. The iteration order here can in computeSubClasses()
1065 if (A->getMembers().size() == B->getMembers().size()) in getMatchingSubClassWithSubRegs()
1067 return A->getMembers().size() > B->getMembers().size(); in getMatchingSubClassWithSubRegs()
1072 // Find all the subclasses of this one that fully support the sub-register in getMatchingSubClassWithSubRegs()
1077 BitVector SuperRegRCsBV = BiggestSuperRegRC->getSubClasses(); in getMatchingSubClassWithSubRegs()
1106 // exists that contains all the 32-bit subregisters because GR64 contains RIP in getMatchingSubClassWithSubRegs()
1115 if (SuperRegClassBV[SuperRegRC->EnumValue]) { in getMatchingSubClassWithSubRegs()
1120 // SubRegRC that don't have super registers via SubIdx. Keep looking to in getMatchingSubClassWithSubRegs()
1128 if (SuperRegRC->getMembers().size() >= SubRegRC->getMembers().size()) in getMatchingSubClassWithSubRegs()
1147 for (CodeGenRegisterClass *RC : FindI->second) in getSuperRegClasses()
1148 Out.set(RC->EnumValue); in getSuperRegClasses()
1151 // Populate a unique sorted list of units from a register set.
1165 //===----------------------------------------------------------------------===//
1167 //===----------------------------------------------------------------------===//
1171 : TheDef(R), Name(std::string(R->getName())) { in CodeGenRegisterCategory()
1172 for (Record *RegClass : R->getValueAsListOfDefs("Classes")) in CodeGenRegisterCategory()
1176 //===----------------------------------------------------------------------===//
1178 //===----------------------------------------------------------------------===//
1189 // Read in the user-defined (named) sub-register indices. in CodeGenRegBank()
1201 if (!Regs.empty() && Regs[0]->isSubClassOf("X86Reg")) { in CodeGenRegBank()
1238 // register-register references. in CodeGenRegBank()
1245 // causes some failures in MIPS - perhaps they have duplicate register name in CodeGenRegBank()
1246 // entries? (or maybe there's a reason for it - I don't know much about this in CodeGenRegBank()
1247 // code, just drive-by refactoring) in CodeGenRegBank()
1249 std::pair(Reg.TheDef->getValueAsString("AsmName"), &Reg)); in CodeGenRegBank()
1251 // Precompute all sub-register maps. in CodeGenRegBank()
1252 // This will create Composite entries for all inferred sub-register indices. in CodeGenRegBank()
1267 // Infer even more sub-registers by combining leading super-registers. in CodeGenRegBank()
1272 // After the sub-register graph is complete, compute the topologically in CodeGenRegBank()
1277 // For each pair of Reg:SR, if both are non-artificial, mark the in CodeGenRegBank()
1278 // corresponding sub-register index as non-artificial. in CodeGenRegBank()
1284 if (!SR->Artificial) in CodeGenRegBank()
1285 P.first->Artificial = false; in CodeGenRegBank()
1298 // Allocate user-defined register classes. in CodeGenRegBank()
1354 if (Record *Def = RC->getDef()) in addToMaps()
1363 // Create a synthetic sub-class if it is missing.
1368 // Synthetic sub-class has the same size and alignment as RC. in getOrCreateSubClass()
1369 CodeGenRegisterClass::Key K(Members, RC->RSI); in getOrCreateSubClass()
1372 return FoundI->second; in getOrCreateSubClass()
1374 // Sub-class doesn't exist, create a new one. in getOrCreateSubClass()
1384 PrintFatalError(Def->getLoc(), "Not a known RegisterClass!"); in getRegClass()
1391 CodeGenSubRegIndex *Comp = A->compose(B); in getCompositeSubRegIndex()
1396 std::string Name = A->getName() + "_then_" + B->getName(); in getCompositeSubRegIndex()
1397 Comp = createSubRegIndex(Name, A->getNamespace()); in getCompositeSubRegIndex()
1398 A->addComposite(B, Comp, getHwModes()); in getCompositeSubRegIndex()
1408 assert(Idx->ConcatenationOf.empty() && "No transitive closure?"); in getConcatSubRegIndex()
1418 std::string Name = Parts.front()->getName(); in getConcatSubRegIndex()
1419 const unsigned UnknownSize = (uint16_t)-1; in getConcatSubRegIndex()
1423 Name += Parts[i]->getName(); in getConcatSubRegIndex()
1426 Idx = createSubRegIndex(Name, Parts.front()->getNamespace()); in getConcatSubRegIndex()
1427 Idx->ConcatenationOf.assign(Parts.begin(), Parts.end()); in getConcatSubRegIndex()
1435 const SubRegRange &FirstPartRange = Part->Range.get(M); in getConcatSubRegIndex()
1443 Name += Part->getName(); in getConcatSubRegIndex()
1445 const SubRegRange &PartRange = Part->Range.get(M); in getConcatSubRegIndex()
1456 unsigned Offset = IsContinuous ? FirstPartRange.Offset : -1; in getConcatSubRegIndex()
1457 Idx->Range.get(M) = SubRegRange(Size, Offset); in getConcatSubRegIndex()
1466 // Subreg -> { Reg->Reg }, where the right-hand side is the mapping from in computeComposites()
1467 // register to (sub)register associated with the action of the left-hand in computeComposites()
1486 C.insert({P.first, F->second}); in computeComposites()
1494 // this could flag false positives. We're interested in non-vacuous in computeComposites()
1500 if (F == Map2.end() || P.second != F->second) in computeComposites()
1521 TopoSigs.set(Reg1.getTopoSig()); in computeComposites()
1530 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1540 assert(Idx3 && "Sub-register doesn't have an index"); in computeComposites()
1544 Idx1->addComposite(Idx2, Idx3, getHwModes())) { in computeComposites()
1545 // If the composition was not user-defined, always emit a warning. in computeComposites()
1548 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() + in computeComposites()
1549 " and " + Idx2->getQualifiedName() + in computeComposites()
1550 " compose ambiguously as " + Prev->getQualifiedName() + in computeComposites()
1551 " or " + Idx3->getQualifiedName()); in computeComposites()
1559 // sub-register index level. Each bit in the lane mask is like a register unit
1560 // class, and two lane masks will have a bit in common if two sub-register
1563 // Conservatively share a lane mask bit if two sub-register indices overlap in
1608 // the mask is set. in computeSubRegLaneMasks()
1611 // Skip non-leaf subregisters. in computeSubRegLaneMasks()
1617 if (NextBit < LaneBitmask::BitWidth - 1) in computeSubRegLaneMasks()
1625 const CodeGenSubRegIndex *Composite = C->second; in computeSubRegLaneMasks()
1627 assert(Composite->getComposites().empty()); in computeSubRegLaneMasks()
1630 unsigned DstBit = Composite->LaneMask.getHighestLane(); in computeSubRegLaneMasks()
1631 int Shift = DstBit - SrcBit; in computeSubRegLaneMasks()
1647 // Optimize if the transformation consists of one step only: Set mask to in computeSubRegLaneMasks()
1662 // FIXME: What if ad-hoc aliasing introduces overlaps that aren't represented in computeSubRegLaneMasks()
1663 // by the sub-register graph? This doesn't occur in any known targets. in computeSubRegLaneMasks()
1668 // If some super-registers without CoveredBySubRegs use this index, we can in computeSubRegLaneMasks()
1683 // For classes without any subregisters set LaneMask to 1 instead of 0. in computeSubRegLaneMasks()
1698 // is a set of connected components.
1705 // A Weight field caches the max per-register unit weight in each UberRegSet.
1707 // A set of SingularDeterminants flags single units of some register in this set
1708 // for which the unit weight equals the set weight. These units should not have
1720 // Partition registers into UberRegSets, where each set is the transitive
1723 // UberRegSets[0] is a special non-allocatable set.
1744 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue); in computeUberSets()
1747 AllocatableRegs.set((*Regs.begin())->EnumValue); in computeUberSets()
1749 AllocatableRegs.set(CGR->EnumValue); in computeUberSets()
1750 UberSetIDs.join(USetID, CGR->EnumValue); in computeUberSets()
1753 // Combine non-allocatable regs. in computeUberSets()
1763 // Make the first UberSet a special unallocatable set. in computeUberSets()
1766 // Insert Registers into the UberSets formed by union-find. in computeUberSets()
1778 USet->Regs.push_back(&Reg); in computeUberSets()
1786 // Skip the first unallocatable set. in computeUberWeights()
1791 // Initialize all unit weights in this set, and remember the max units/reg. in computeUberWeights()
1794 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) { in computeUberWeights()
1812 if (I->Weight != MaxWeight) { in computeUberWeights()
1813 LLVM_DEBUG(dbgs() << "UberSet " << I - UberSets.begin() << " Weight " in computeUberWeights()
1816 : I->Regs) dbgs() in computeUberWeights()
1817 << " " << Unit->getName(); in computeUberWeights()
1819 // Update the set weight. in computeUberWeights()
1820 I->Weight = MaxWeight; in computeUberWeights()
1824 for (const auto R : I->Regs) { in computeUberWeights()
1825 if (R->getRegUnits().count() == 1 && R->getWeight(RegBank) == I->Weight) { in computeUberWeights()
1826 I->SingularDeterminants |= R->getRegUnits(); in computeUberWeights()
1834 // UberSet. Self-recursion processes the subregister tree in postorder so
1838 // - creates new adopted register units
1839 // - causes superregisters to inherit adopted units
1840 // - increases the weight of "singular" units
1841 // - induces recomputation of UberWeights.
1848 NormalRegs.resize(std::max(Reg->EnumValue + 1, NormalRegs.size())); in normalizeWeight()
1849 if (NormalRegs.test(Reg->EnumValue)) in normalizeWeight()
1851 NormalRegs.set(Reg->EnumValue); in normalizeWeight()
1854 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); in normalizeWeight()
1857 continue; // self-cycles happen in normalizeWeight()
1865 if (Reg->inheritRegUnits(RegBank)) in normalizeWeight()
1871 unsigned RegWeight = Reg->getWeight(RegBank); in normalizeWeight()
1872 if (UberSet->Weight > RegWeight) { in normalizeWeight()
1874 // for this register, has not been used to normalize a subregister's set, in normalizeWeight()
1876 unsigned AdjustUnit = *Reg->getRegUnits().begin(); in normalizeWeight()
1877 if (Reg->getRegUnits().count() != 1 || NormalUnits.test(AdjustUnit) || in normalizeWeight()
1878 UberSet->SingularDeterminants.test(AdjustUnit)) { in normalizeWeight()
1880 AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight); in normalizeWeight()
1881 Reg->adoptRegUnit(AdjustUnit); in normalizeWeight()
1882 // Adopting a unit does not immediately require recomputing set weights. in normalizeWeight()
1886 RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight); in normalizeWeight()
1887 // The unit may be shared among sets and registers within this set. in normalizeWeight()
1894 NormalUnits |= Reg->getRegUnits(); in normalizeWeight()
1927 // Find a set in UniqueSets with the same elements as Set.
1931 const RegUnitSet &Set) { in findRegUnitSet() argument
1933 [&Set](const RegUnitSet &I) { return I.Units == Set.Units; }); in findRegUnitSet()
1946 /// special-purpose register subsets, such as tail-call and Thumb
1950 /// the allocatable registers and marking other classes as non-allocatable and
1951 /// (2) having a way to mark special purpose classes as "don't-care" classes for
1955 /// set limit by filtering the reserved registers.
1958 /// Q-tuples with ssub index 0 include all S regs but also include D16+. We
1959 /// should not expand the S set to include D regs.
1981 // We can pick any of the set names for the merged set. Go for the in pruneUnitSets()
2059 assert(Idx < (2 * NumRegUnitSubSets) && "runaway unit set inference"); in computeRegUnitSets()
2106 int RCIdx = -1; in computeRegUnitSets()
2135 "missing unit set for regclass"); in computeRegUnitSets()
2175 // Ignore non-leaf subregisters, their lane masks are fully covered by in computeRegUnitLaneMasks()
2177 if (!SubReg->getSubRegs().empty()) in computeRegUnitLaneMasks()
2181 LaneBitmask LaneMask = SubRegIndex->LaneMask; in computeRegUnitLaneMasks()
2183 for (unsigned SUI : SubRegister->getRegUnits()) { in computeRegUnitLaneMasks()
2210 // Compute a unique set of RegUnitSets. One for each RegClass and inferred in computeDerivedInfo()
2221 RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs; in computeDerivedInfo()
2222 RC.CoveredBySubRegs &= Reg->CoveredBySubRegs; in computeDerivedInfo()
2226 // Get the weight of each set. in computeDerivedInfo()
2230 // Find the order of each set. in computeDerivedInfo()
2247 // Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
2261 // Compute the set intersection of RC1 and RC2. in inferCommonSubClass()
2262 const CodeGenRegister::Vec &Memb1 = RC1->getMembers(); in inferCommonSubClass()
2263 const CodeGenRegister::Vec &Memb2 = RC2->getMembers(); in inferCommonSubClass()
2275 // stricter one for sub-classing. If they are equal, prefer RC1. in inferCommonSubClass()
2276 if (RC2->RSI.hasStricterSpillThan(RC1->RSI)) in inferCommonSubClass()
2280 RC1->getName() + "_and_" + RC2->getName()); in inferCommonSubClass()
2285 // Synthesize missing sub-classes for getSubClassWithSubReg().
2287 // Make sure that the set of registers in RC with a given SubIdx sub-register
2288 // form a register class. Update RC->SubClassWithSubReg.
2291 // Map SubRegIndex to set of registers in RC supporting that SubRegIndex. in inferSubClassWithSubReg()
2296 // Compute the set of registers supporting each SubRegIndex. in inferSubClassWithSubReg()
2298 for (const auto R : RC->getMembers()) { in inferSubClassWithSubReg()
2299 if (R->Artificial) in inferSubClassWithSubReg()
2301 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs(); in inferSubClassWithSubReg()
2303 if (!I.first->Artificial) in inferSubClassWithSubReg()
2321 if (I->second.size() == RC->getMembers().size()) { in inferSubClassWithSubReg()
2322 RC->setSubClassWithSubReg(&SubIdx, RC); in inferSubClassWithSubReg()
2327 RC, &I->second, RC->getName() + "_with_" + I->first->getName()); in inferSubClassWithSubReg()
2328 RC->setSubClassWithSubReg(&SubIdx, SubRC); in inferSubClassWithSubReg()
2333 // Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
2335 // Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
2351 if (RC->getSubClassWithSubReg(&SubIdx) != RC) in inferMatchingSuperRegClass()
2354 // Build list of (Super, Sub) pairs for this SubIdx. in inferMatchingSuperRegClass()
2357 for (const auto Super : RC->getMembers()) { in inferMatchingSuperRegClass() local
2358 const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second; in inferMatchingSuperRegClass()
2359 assert(Sub && "Missing sub-register"); in inferMatchingSuperRegClass()
2360 SubToSuperRegs[Sub].push_back(Super); in inferMatchingSuperRegClass()
2361 TopoSigs.set(Sub->getTopoSig()); in inferMatchingSuperRegClass()
2364 // Iterate over sub-register class candidates. Ignore classes created by in inferMatchingSuperRegClass()
2382 const std::vector<const CodeGenRegister *> &SuperRegs = It->second; in inferMatchingSuperRegClass()
2392 if (SubSetVec.size() == RC->getMembers().size()) { in inferMatchingSuperRegClass()
2400 RC->getName() + "_with_" + SubIdx.getName() + "_in_" + in inferMatchingSuperRegClass()
2415 // Use one-before-the-end so it doesn't move forward when new elements are in computeInferredRegisterClasses()
2423 if (RC->Artificial) in computeInferredRegisterClasses()
2437 // to match old super-register classes with sub-register classes created in computeInferredRegisterClasses()
2451 /// getRegisterClassForRegister - Find the register class that contains the
2454 /// superset-subset relationship and the same set of types, return the
2471 if (RC.getValueTypes() != FoundRC->getValueTypes()) in getRegClassForRegister()
2485 if (FoundRC->hasSubClass(&RC)) in getRegClassForRegister()
2502 (!BestRC || BestRC->hasSubClass(&RC))) in getMinimalPhysRegClass()
2511 SetVector<const CodeGenRegister *> Set; in computeCoveredRegisters() local
2513 // First add Regs with all sub-registers. in computeCoveredRegisters()
2516 if (Set.insert(Reg)) in computeCoveredRegisters()
2517 // Reg is new, add all sub-registers. in computeCoveredRegisters()
2518 // The pre-ordering is not important here. in computeCoveredRegisters()
2519 Reg->addSubRegsPreOrder(Set, *this); in computeCoveredRegisters()
2522 // Second, find all super-registers that are completely covered by the set. in computeCoveredRegisters()
2523 for (unsigned i = 0; i != Set.size(); ++i) { in computeCoveredRegisters()
2524 const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs(); in computeCoveredRegisters()
2526 const CodeGenRegister *Super = SR[j]; in computeCoveredRegisters() local
2527 if (!Super->CoveredBySubRegs || Set.count(Super)) in computeCoveredRegisters()
2529 // This new super-register is covered by its sub-registers. in computeCoveredRegisters()
2531 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); in computeCoveredRegisters()
2533 if (!Set.count(I.second)) { in computeCoveredRegisters()
2537 // All sub-registers in Set, add Super as well. in computeCoveredRegisters()
2538 // We will visit Super later to recheck its super-registers. in computeCoveredRegisters()
2540 Set.insert(Super); in computeCoveredRegisters()
2546 for (unsigned i = 0, e = Set.size(); i != e; ++i) in computeCoveredRegisters()
2547 BV.set(Set[i]->EnumValue); in computeCoveredRegisters()
2553 dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName(); in printRegUnitName()