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1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
67 // Basic 64-bit capable CPU.
247 // 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
250 // listed here before, which means it doesn't support -march, -mtune and so on.
252 // cpu_dispatch/specific() feature and -march, -mtune, and so on.
253 // clang-format off
258 // i386-generation processors.
260 // i486-generation processors.
262 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX, '\0', false },
265 // i586-generation processors, P5 microarchitecture based.
268 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
270 // i686-generation processors, P6 / Pentium M microarchitecture based.
280 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
282 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
284 // Netburst microarchitecture based processors.
291 // Core microarchitecture based processors.
304 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
307 // Nehalem microarchitecture based processors.
311 // Westmere microarchitecture based processors.
314 // Sandy Bridge microarchitecture based processors.
317 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, '\0', false },
318 // Ivy Bridge microarchitecture based processors.
321 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, '\0', false },
322 // Haswell microarchitecture based processors.
324 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, '\0', false },
327 // Broadwell microarchitecture based processors.
331 // Skylake client microarchitecture based processors.
333 // Skylake server microarchitecture based processors.
334 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false },
337 // Cascadelake Server microarchitecture based processors.
339 // Cooperlake Server microarchitecture based processors.
341 // Cannonlake client microarchitecture based processors.
343 // Icelake client microarchitecture based processors.
344 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, '\0', false },
346 // Rocketlake microarchitecture based processors.
348 // Icelake server microarchitecture based processors.
349 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, '\0', false },
351 // Tigerlake microarchitecture based processors.
353 // Sapphire Rapids microarchitecture based processors.
355 // Alderlake microarchitecture based processors.
357 // Raptorlake microarchitecture based processors.
359 // Meteorlake microarchitecture based processors.
361 // Arrowlake microarchitecture based processors.
363 { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false },
365 // Lunarlake microarchitecture based processors.
367 // Gracemont microarchitecture based processors.
369 // Pantherlake microarchitecture based processors.
371 // Sierraforest microarchitecture based processors.
373 // Grandridge microarchitecture based processors.
375 // Granite Rapids microarchitecture based processors.
377 // Granite Rapids D microarchitecture based processors.
378 …{ {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512FP16, FeaturesGraniteRapids | FeatureAMX_C…
380 // Emerald Rapids microarchitecture based processors.
382 // Clearwaterforest microarchitecture based processors.
389 // Lakemont microarchitecture based processors.
393 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | FeaturePRFCHW, '\0', false },
394 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | FeaturePRFCHW, '\0', false },
397 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
398 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
399 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
400 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
404 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8, '\0', false },
406 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
407 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
408 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
425 // Generic 64-bit processor.
426 { {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
427 { {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false },
428 { {"x86-64-v3"}, CK_x86_64_v3, FEATURE_AVX2, FeaturesX86_64_V3, '\0', false },
429 { {"x86-64-v4"}, CK_x86_64_v4, FEATURE_AVX512VL, FeaturesX86_64_V4, '\0', false },
433 // clang-format on
435 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
590 // SSE4_A->FMA4->XOP chain.
651 FeatureBitset Bits = I->Features; in getFeaturesForCPU()
653 // Remove the 64-bit feature which we only use to validate if a CPU can in getFeaturesForCPU()
654 // be used with 64-bit mode. in getFeaturesForCPU()
674 if (Bits[--i]) in getImpliedEnabledFeatures()
708 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures); in updateImpliedFeatures()
723 assert(I->Mangling != '\0' && "Processor dooesn't support function multiversion!"); in getCPUDispatchMangling()
724 return I->Mangling; in getCPUDispatchMangling()
746 FeatureMask[Feature / 32] |= 1U << (Feature % 32); in getCpuSupportsMask()
754 // "compat" features are assigned non-duplicate consecutive priorities in getFeaturePriority()
755 // starting from one (1, ..., 37) and multiple zeros. in getFeaturePriority()
762 std::iota(HelperList.begin(), HelperList.begin() + MaxPriority + 1, 0); in getFeaturePriority()
763 for (size_t i = MaxPriority + 1; i != std::size(Priorities); ++i) in getFeaturePriority()
776 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); in getFeaturePriority()